The aim of this work is to understand charge loss mechanisms in TANOS stack for which charge retention is monitored just after programming in an almost continuous way and voltage is applied during retention experiments in order to obtain zero electric field either on alumina or tunnel oxide. The charge loss mechanisms in TANOS stack can be a quite complicated process: An initial fast DT from interface traps localized at SiN/alumina interface, followed by charge loss through alumina from bulk traps in SiN which influences charge redistribution towards the tunnel oxide, observed only in Si-rich SiN. Programming voltage and stack composition impact trapped charge localization and hence charge redistribution and charge loss, even if the same initial Vfb is considered in charge retention experiments. While the charge loss through tunnel oxide is a DT, the charge loss through alumina depends on temperature and it is the main component of the charge loss in retention experiments for longer time.

The aim of this work is to investigate the physical mechanisms behind the write/erase and retention performances of band gap engineering (BE) layers used as tunnel oxide in charge trap memory stack. The investigation of the BE layers alone will be completed with the analyses of its integration within a TANOS (TaN/Alumina/Nitride/Oxide/Silicon) stack, pointing out the correlation between electrical performance and reliability limits.Good write/erase/retention performances can be achieved with BE tunnel oxide by using silicon nitride layer integrated in SiO2-Si3N4-SiO2 stack, as long as all different mechanisms are taken into account in optimizing stack composition: hole injection which improves erase efficiency, charge trapping and detrapping from the thin silicon nitride which causes program instabilities and initial charge loss which does not significantly impact long term retention. All these phenomena make very crucial the BE tunnel process control and difficult its use for multi-level application. (C) 2011 Elsevier B.V. All rights reserved.

In this paper, a study of a La-based high-k oxide to be employed as blocking oxide in future non-volatile scaled memory devices is presented. Hf1-xLaxOy deposited by atomic layer deposition is considered. In order to allow the integration of this material, its chemical interaction with an Al2O3 cap layer has been studied. Moreover, the electrical characteristics have been evaluated after integration in capacitor structures. The rare earth-based ternary oxide presents promising characteristics to be a good candidate as active dielectric for non volatile memory devices.

The aim of this work is to study the impact of silicon nitride deposition/treatment technologies on charge trap (CT) nonvolatile memory performances. The authors have found that the technology modifies the charge trapping behavior with a one to one correlation between write/erase and charge retention characteristics. In particular, they used rapid thermal chemical vapor deposition techniques to obtain films with different compositions, but they were not able to improve CT performances with respect to standard low pressure chemical vapor deposition (LPCVD). Besides, an in situ steam generated treatment applied to standard LPCVD silicon nitride modifies the film properties inducing a lower programming efficiency, but improving charge retention characteristics.

In this work, Conductive Atomic Force Microscope (CAFM) experiments have been combined with device level measurements to evaluate the impact of an electrical stress applied on MOS structures with a 9.8nm thick SiO2 layer for memory devices. Charge trapping in the generated defects and leakage current measured at the nanoscale have been correlated to the measurements obtained on fully processed MOS structures.

A study of a La-based high-k oxide to be employed as active dielectric in future scaled memory devices is presented. The focus will be held on LaxZr1−xO2−δ (x=0.25) compound. In order to allow the integration of this material, its chemical interaction with an Al2O3 cap layer has been studied. Moreover, the electrical characteristics of these materials have been evaluated integrating them in capacitor structures. The rare earth-based ternary oxide is demonstrated to be a promising candidate for future non-volatile memory devices based on charge trapping structure.

Aim of this work is to investigate the degradation of n-MOS transistor when stressed at high fields, typical operating condition when used as a pump in non-volatile memory (NVM) application. It is possible to understand where the main degradation occurs studying the degradation in different structures as a function of the stress field. Besides, the impact of different isolation processes is considered, pointing out what is the most critical issue for the degradation. Simulations of the conduction mechanism allow the fitting of the transfer characteristics of virgin transistor, while the stressed one can be described only assuming the localization of oxide positive and negative trapped charge whose amount depends on the field configuration.

Aim of this work is to investigate the conduction characteristics of different high-K dielectrics deposited by ALD technique. A novel methodology which allows the evaluation of very low leakage current at least two-orders lower than standard I–V characteristics with a reduced 3-masks process flow has been used. A comparison with standard ONO technology is performed and shows that the Al2O3 layer is the most promising candidate for ONO replacement. Different techniques for depositing this layer have been compared investigating the impact of subsequent thermal treatments, which greatly improve Al2O3 performances.

Aim of this work is the investigation of Random Telegraph Signal (RTS) in Flash memory cell. Current fluctuations have been performed also as a function of temperature in order to characterize the nature of traps responsible for noise in relatively thick tunnel oxide. Trap energy level and spatial localization from the Si/SiO2 interface has been determined. The impact of stress has been also investigated showing no significant noise increase in single cell. This has been ascribed to the tunnel oxide technology whose heavy nitridation allows minimizing the degradation of the region responsible for RTS in Flash memory cell.

Aim of this work is to study the reliability of the dielectric between cell control gate and drain contact. Conduction characteristics and reliability under high field stress are investigated. The large spread in this dielectric thickness because of mask misalignment makes the usual reliability procedures very difficult to be applied. Results relative to fast and long reliability measurements are discussed, proposing a method for the evaluation of the spread between control gate and drain contact. Moreover, this methodology allows a screening of the structures with a too critical mask misalignment, or with a poor dielectric quality which could cause memory failures during cycling

Aim of this work is to propose a new fast methodology to be applied to thick gate and tunnel oxides in Flash and embedded Flash processes. Starting from the reliability characterization of the dielectric it is possible to define a very short stress (lower than 1-2sec) which correlates with standard long reliability testing procedures (constant voltage stress, CVS, or constant current stress, CCS). For thick dielectrics, whose significant charge trapping affects the lifetime, the definition of a short stress condition is critical, but it is shown that a short CCS test can overcome this problem. This short test can be introduced at parametric testing in order to screen defective oxides following a criteria directly correlated with device requirements

A key issue for Flash cell scaling down is the reduction of tunnel oxide thickness limited by the higher gate leakage current (Stress Induced Leakage Current, SILC) after cycling. It is possible to reduce the oxide degradation during cycling by reducing the stress pulse duration and increase the time between pulses. This allows the annealing of precursor sites with an overall reduction of stable traps. Aim of this work is the investigation of the SILC induced by pulsed stress and the corresponding charge trapped in the oxide during stress. The impact of the oxidation technology will also be discussed.