In this study a temperature-dependent creep characterization of SAC405 solder alloy was performed, with the aim of its implementation into thermomechanical finite element (FE) models. The creep behavior of solder interconnects for wafer level packaging was investigated using the constant force nanoindentation method. Nanoindentation was performed in a temperature range from -55 degrees C to 175 degrees C, which covers automotive operational conditions as well as standard test and qualification requirements. It was found that a single Garofalo creep model cannot predict creep rates for the whole investigated temperature range with acceptable accuracy due to potential creep mechanism change at temperatures above +125 degrees C. Hence, the bipartite Garofalo model, which contains eight material constants, was proposed to depict the high-temperature creep behavior of the SAC405 alloy. Material constants are presented in the article. The proposed model was implemented in a thermomechanical FE simulation of a temperature cycling (TC) test. The TC reliability test was performed using a specially designed bump-on-pad (BoP) test structure with different bump population densities. The Weibull analysis was performed, and characteristic life was defined for fully populated and depopulated package layouts: 607 +/- 21 and 591 +/- 32 cycles, respectively. The FE model setup is described in detail, and recommendations are made to achieve higher accuracy in the simulation outcome. Implementation of these recommendations in combination with the derived bipartite Garofalo creep model enabled simulations to precisely predict the interconnect failure mode and depict differences in TC stress with different package layouts. As a result, the maximum creep strain in SAC405 interconnect accumulated per one temperature cycle was 14% higher for the depopulated bump layout configuration. This result confirms an inverse correlation between calculated accumulated creep strain and characteristic life. In addition, an FE comparative analysis of Anand, bipartite Garofalo, and conventional Garofalo models is discussed.

The simulation support for design of power electronics is highly required due to safe time to market, to handle the materials and the architecture complexity and to reach the required reliability. Detailed material models of Ag-sintered joints for use in simulations (FEA), especially for thermo-mechanical stability studies, make a valuable contribution. The authors determined material models with the nonlinearities as time and temperature effects in Ag sintering joints for FEA analysis. Further, mechanical measurements of thermo-mechanical behavior due to influences of microstructure formation, such as porosity (and distribution) is shown. Process parameter variations lead to variability of porosity and has been investigated on chip bonding as well as on lap shear specimen for mechanical measurements.

A modern development process of lifetime prediction for reliable electronics uses numerically prepared failure data from accelerated thermal-cycling aging experiments. In this type of experiment, soldered assemblies are subjected to a temperature cycling load and damaged by low cycle fatigue procedure. The solder joints of this LGA-like assembly are stressed by an increased temperature range to accelerate the degradation of the solder alloy material and initiates the change of microstructure and crack propagation. Creep mechanisms in SAC-based solder alloys are activated at the temperature ranges of 150 °C to -40 °C. Tests without accelerated conditions take too much experimental time and costs until reaching mean time to failure. On the other hand, the level of acceleration due to an increased temperature range is limited by the package materials and damage mechanisms. The major challenge is to transfer these accelerated failure data to a lifetime estimation under field conditions, which operates in reduced temperature range. Electronic designers require the acceleration factors or lifetime estimation data to adapt suited, reliable electronic to field condition of electronics in services.

In this paper, the analysis of the board level reliability of a Radar package continuously studied in parallel to its progressing design development will be presented. In general, the studied Radar package follows the concept of an interposer-like antenna board, carrying the Radar antenna patch but also connecting the Radar device to the PCB in BGA manner. The signal processor and antenna driver ICs are packaged in a fan-out wafer level package that is assembled to the antenna board as a BGA land side package. The board level reliability of the Radar device was investigated considering variations of the package design and package and interconnect materials. Test conditions were selected in conformance to the AEC-Q100 standard for board level reliability testing. Intermediate electrical read-outs were executed to monitor the sample health including the check of single I/Os at different I/O locations with regard to the BGA grid. As of now, all antenna board configurations were tested for at least 1,000 temperature shock test cycles. Selected configurations reached 3,000 cycles. In these tests, Radar demonstrator samples achieved a characteristic TCoB life of more than 2,000 cycles. Solder fatigue behaviour was found to be the root failure cause.

The stress related shifts of transistors are measured by precise stress application with a newly designed in-situ four-point bending (4PB) system. A test board including a flip chip packaged test vehicle is loaded with uniaxial stress. The test vehicle contains dedicated ring oscillator circuits fabricated in the 22 nm FDSOI technology node, used to evaluate the effects of thermo-mechanical stress on the characteristics of CMOS devices. Finite element simulation provides insight into the originated stress values in the board, package, and active devices during mechanical loading. Considering the bending caused stress in the devices and the specific layout of the circuits, the directional frequency shifts of the circuits under stress are derived. These shifts are compared with a previous indentation study, which has been developed to induce very localized loads. The comparison aims for verification of the indentation approach to study directional stress related effects as well as very localized effects in chip stacks.

The stress-related change in the characteristics of transistors manufactured in the 22 nm fully depleted silicon on insulator (FDSOI) CMOS technology node is studied with advanced experimental indentation setups. Precisely, NAND and NOR ring oscillator circuits are used to monitor the strain-caused mobility deviations in the silicon transistor channels. Piezoresistive coefficients for strained silicon are calculated from the experimental indentations data using spherical and cylindrical tip geometries. In contrast to spherical tips, the cylindrical indentation tips enable to induce the stress more selectively into a desired direction. To set up the experimental details appropriately, finite element (FE) simulations have been used. Additionally, FE method (FEM) studies are conducted to compute the quantitative strain values in the silicon transistor channels as a function of contact load as well as chip and tip geometries. Using the signal deviations of the RO circuits subjected to strain from spherical and cylindrical indentation, a set of equations using the linearized piezoresistive model are created to determine the directional piezoresistive coefficients.

The strain impact on integrated circuit performance is investigated by applying a novel indentation technique. The approach aims to investigate stress caused by CPI, particularly highly localized stress/strain with respect to the actual device geometry. Non-destructive elastic indentation is used to induce homogenous stress fields in the vicinity of the test structure by applying a contact with a spherical tip. Strain-sensitive ring oscillator structures manufactured in the 22 nm FDSOI CMOS technology node are designed to monitor the device and simultaneously the NMOS and PMOS strain behavior separately. Complementary FE-simulations provide a deeper insight into the obtained experimental results by transferring them from contact force into the stress/strain space and validating the indentation approach. Relevant layout and indentation dependent parameters are investigated and evaluated. The simulation of the strain-induced mobility shift and the comparison with the established correlation verifies the accuracy of the approach. The results provide an insight into package-related stress and resulting transistor degradation, aiming at establishing a versatile tool to estimate the effect of specific real-usage conditions.

This paper presents a numerical comparison of stress-strain conditions in solder joints by the application of a unified primary-secondary creep model and state of the art stationary creep model approach. Both extracted material models are fitted on the same set of solder material and measurement results, taken by the authors. So, individual setup influences stay constant. The first model is the commonly utilized Garofalo approach based on a hyperbolic-sine equation [1], the other is a unified viscoplastic constitutive model based on propositions by Chaboché et al. Both material models allow the calculation of mechanical stress and strain condition in dependency on temperature from $- 40^{\circ}\mathrm{C}$ to $150^{\circ}\mathrm{C}$ and strain rates from 1e-6/s to 1e-3/s. Differences in modelling occur in the degree of freedom to integrate materials effects, such as relaxation, stress recovery and hardening. The characterization measurement setup and extraction of material properties has been shown in previous publications [1], [3]. Previous work also already indicated the importance of primary creep, however the vastness of the effect towards component sizes and types is yet to be shown. Therefore a finite-element study has been conducted here to analyze the influence of the modelling approaches in thermo-mechanical application. Geometries of various 2-Pole-SMT components and BGA components have been used. The resulting stress and creep strain progressions in the solder joints are shown for every component. Generally higher strains and lower stresses have been registered with the unified model. The comparison of the resulting strain portions per cycle on a typical chip resistor shows that the accumulated strain increases by approx. 20 % for the unified approach. This difference also largely occurs in the meniscus region of the joints. The results for the BGA variations indicate a 50% increased accumulated strain for the unified approach. Interestingly the bottom portion of the joint towards the substrate pad exhibited heavy increases. For both components the deviations between both modelling approaches are not small or negligible. The work presented here has shown that only the unified model is able to fully describe the primary and the secondary creep state throughout the whole temperature range. The unified model almost identically follows the measured behavior. Hence the stress and strain situation around the solder joint can be modelled more accurately. This is especially important when the joints are surrounded by other rather stiff materials (e.g. IMS or ceramic substrates). Only an accurate solder-modelling can lead to correct damage behavior assumptions. Also only with the correct assumptions and accurate strain calculations a reliable lifetime-model can be established.

The impact of strain, induced by nanoindentation, on integrated circuit performance is measured. Localized strain caused by chip- package interaction alters the charge carrier mobility in the transistor channel due to the piezoresistive effect. Instrumented indentation enables to induce controlled localized loads with high lateral precision, and it is used to apply consecutive loading conditions to a single test device. Newly designed ring oscillator test structures manufactured in 22 nm FDSOI technology are used as a sensor to monitor the strain effect on transistor performance. Novel tip geometries provide insight into the direction dependent strain impact. Strain/stress fields at transistor level are determined by complementary FEM simulation. Board bending experiments with uniaxial stress/strain conditions are performed to verify the approach. The established correlation of mechanical load and device performance is used to provide an estimate for the effect of package related stress on transistor performance.

As of today, various solutions to handle the dissipating heat of power electronics devices are available. These include the application of heatsinks, overmolding, embedding of components into substrates, use of substrates with embedded metal or ceramic heatsinks or liquid cooling approaches. When it comes to power electronics for high voltages and fast switching the parasitic capacity has to be considered. This parasitic capacity affects the electrical performance and may finally even lead to damage of the device. Embedding of metal heatsinks or mounting a substrate to a metal heatsink can even increase the parasitic capacity and hence, worsen the scenario. In this project a rectifier had to be built suitable for voltages of up to 20 kV and switching frequencies of 100 kHz while achieving a low parasitic capacity of max. 3 pF. High voltage diodes were selected to meet the electrical requirements. To fullfil both the thermal and capacitance demands the diodes were embedded into a substrate made from a highly thermal conductive FR4 material. In addition, the substrate is mounted to a ceramic heatsink to enable a superior cooling but to limit the parasitic capacity at the same time. This setup was characterised for its thermal management behaviour in the as build state. Though the lamination of the substrate to the ceramic heatsink showed some challenges its cooling performance could be assessed. Subsequently, the system without the ceramic heatsink was exposed to temperature shock cycles at -40/+125°C for up to 2,000 cycles to analyse the long term stability of the system behaviour. For the repeated investigation of the thermal behaviour and the structural integrity of the system a novel analysis approach using an infrared camera was applied. Cross sections were done in addition to verify the results from the novel thermal analysis approach. As of now no thermo-mechanical damage of the rectifier could be observed proving the ability of the embedding approach and the validity of the results gained with the novel non-destructive analysis approach.

This work focuses on the reliability needs which are caused by the use of recent package solutions for harsh environmental use cases such as assisted or autonomous driving. Simultaneous thermal and mechanical loading of highly integrated packages as Flip-Chip (FC) packages has to be considered, investigated and understood. An earlier introduced test approach used to investigate CR0805 solder joints under combined loading was modified to enable the analysis of FC solder joints. Thus, investigations of solder joint geometries of FC, CSP and BGA packages are now possible. In this work, results on the fatigue behaviour of SnAgCu FC solder joints will be shown. The experiments were conducted under varied harmonic vibration amplitudes at room temperature. A 4.6 x 2.6 mm(2) bare die FC package with a 5 x 5 interconnection grid was tested. Bump size, pad diameter and stand-off are 370 jam, 330 lam and 280 lam, respectively. The damage and fatigue behaviour of the FC solder joints was examined using cross sections. First, test results show damage of solder joints stressed with a peak-to peak deflection of 1.6 mm for up to 75 Million cycles at room temperature. The damage occurred within the solder volume in very close proximity to or at the substrate pad intermetallic interface. Further tests considering varied stress levels are ongoing.

This paper presents a comparison of three different material models, which are currently used to describe creep behaviour of solder alloys in thermo-mechanical use cases. The first model is the commonly utilized Garofalo approach. This approach is based on a hyperbolic-sine equation to describe the secondary (stationary) creep rates dependent on the mechanical stress in combination with the Arrhenius equation to consider temperature dependencies. The other two material models cover the primary and the secondary creep stage. Here, unified viscoplastic constitutive models initially proposed by Anand and Chaboché et al. are introduced. In the presented FEM study result comparison has been done for the accumulated solder joint strains of a SMT component exposed to thermal cycling. Subsequently, the influence on creep strain progression and service life time estimation has been investigated.

This paper presents a methodology to investigate and correlate the influence of porosity of silver sintered interconnects, e.g. used in power electronics, with their thermo-mechanical deformation behaviour. The proposed methodology includes the development of a shear specimen coming with a single cylindrical shaped silver-sintered joint enabling high resolution deformation measurements, strain rate controlled shear tests and according finite element analysis. The methodology also includes the development and optimization of a customized mechanical test system which is optimized for the measuring of deformations in the sub-micro meter range at high forces up to 500 N ([1], [2]). Furthermore, a multi-level image processing approach was developed to determine the porosity distribution of crosss-ection images of silver sintered joints.

The paper presents details about the adequate experimental determination of the Young's modulus on miniaturized specimens for material used in electronic packaging. The difficulty to determine accurately the Young's modulus is caused by the requirements of representative specimens for the area of electronic packaging. In many cases such specimens, e.g. solder balls, are connected with the issues of inhomogeneous stress distributions, small dimensions, or special gripping requirements, that create a number of challenges to conduct mechanical experiments. In addition there are problems that arise from the nonlinearities in the constitutive behaviour of the material to be characterized, such as creep deformation. Therefore any attempt to accurately determine the Young's modulus needs a case to case consideration of the specific issues for the given specimen and material.

This paper is focused on the thermally-induced thermo-mechanical load in interconnections of electronic products, which are necessary to connect an electronic component on substrate material (such as Printed Circuit Board). In order to improve of the material selection, the Fraunhofer IKTS has developed a measurement setup enabling a cost-efficient material characterization in terms of mechanical and fatigue values. The developed setup is able to measure mechanical quantities on a realistic specimen which is stressed under thermo-mechanical load of predefined magnitude. The setup consists of a construction (load frame) with integrated force and contactless displacement sensors to monitor the changes in strength of a specimen in-situ. The first measurement results present a comparison of the influence of two temperature cycling profiles relevant for automotive electronics industry. The realistic specimen comprising four BGA-like solder joints is subjected to temperature cycles until a substantial structure-mechanical failure is observed. Further, the paper presents the calibration steps necessary to understand the unique force-deformation behaviour of the system as function of temperature.

The paper presents details about the adequate experimental determination of the Young's modulus on miniaturized specimens for material used in electronic packaging. The difficulty to determine accurately the Young's modulus is caused by the requirements of representative specimens for the area of electronic packaging. In many cases such specimens, e.g. solder balls, are connected with the issues of inhomogeneous stress distributions, small dimensions, or special gripping requirements, that create a number of challenges to conduct mechanical experiments. In addition there are problems that arise from the nonlinearities in the constitutive behaviour of the material to be characterized, such as creep deformation. Therefore any attempt to accurately determine the Young's modulus needs a case to case consideration of the specific issues for the given specimen and material.

The following topics are dealt with: integrated circuit interconnections; integrated circuit reliability; three-dimensional integrated circuits; copper; integrated circuit packaging; silicon; wafer level packaging; electronics packaging; and solders.

Here, we present an advanced experimental procedure for determining the properties of a SnAg3.5 solder alloy in the strain range of primary creep under cyclic load and isothermal conditions. The challenge in this experiment is the accurate high-resolution measurement of sample elongation used for a closed-loop control, as well as avoiding the influence of sensor and specimen clamping. We realized reproducible strain rate control within a total specimen elongation of 60 μm. The tensile-compression experiment comprises strain rate variation for three strain amplitudes with integrated relaxation stages followed by a measurement of cyclic fatigue. The strain rate at every strain stage was varied in the range of 1E-3 to 1E-6 per second. At the end of every strain stage a time-limited relaxation experiment is performed, where the specimen's length is kept constant, while the stress evolution is recorded. Finally, the specimen is subjected to cyclic fatigue until a drop of 50 % of the initial materials strength is reached. The total procedure is performed in a temperature range from -40 to 150 °C. We prove the capability of common creep models to map the observed cyclic stress-strain hysteresis as well as stress dependency on strain rate. The results reveal substantial limitations of common stationary creep models and strongly suggest the application of advanced visco-plastic material models for an accurate description of the solder alloy properties. The experimental data presented can be used for the calibration of unified visco-plastic constitutive models initially proposed by Chaboché et al. and further extended during the past two decades.

Electronics for automotive or mobile applications are exposed to vibration and shock loads causing PCB and interposer vibration. This leads to high strain rates within the component solder joints. It is known that solder joints show strain rate dependent yield behaviour [1-4] as well as that the strain rate dependency is dependent on the solder alloy composition. The solder joint alloy composition is determined by the solder paste and/or ball composition and the metallisation of the component and the substrate. There have been numerous publications on the strain rate depending yield behaviour of several alloy compositions used in industry. It has been shown that solder alloys behave more stiff and brittle if there is a higher silver content. Still, the direct dependency of yield behaviour and strain rate sensitivity on the silver and copper content has not been investigated and published yet. In this work the base material Sn99.9 and six lead-free solder alloys namely SnAg1.3 (wt.%), SnAg3.5, SnCu0.5, SnCu0.7, SnCu0.9 and SnAg1.3Cu0.5 have been studied for their yielding behaviour, strain rate sensitivity, deformation and fracture behaviour. Selected alloys have been tested in the as cast and isothermally aged state. The ageing was done at 150°C for 1000 h. Specimens were manufactured by casting applying fast cooling with 50 K/min. The specimen geometry as shown in figure 1 is a miniature dogbone shape to achieve a specimen micro- and grain structure comparable to solder joints. A high deformation speed tester introduced in earlier work [5] was utilised to conduct high strain rate experiments at rates from 20 to 800 s -1 . High resolution online stress measurement revealed the strain rate dependent yielding behaviour. Fracture site inspection giving information on the damage behaviour was done by electron microscopy. The EBSD (electron backscatter diffraction) option was used to analyse the deformation behaviour at the grain structure level. Local fracture strain measurement revealed a very ductile behaviour of all specimens.

Embedding of discrete passives or functional chips as bare dies has been successfully proven in the last years. The embedding technology provides multiple advantages when compared to conventional surface mount technology. As of today multiple possibilities to embed active devices in the substrate exist. One method has been selected here and a fully parameterized finite-element framework has been created to assess its reliability potential. It is shown how it is possible to represent even very complex geometries with features spanning over multiple orders of magnitude, while fulfilling the requirement of reasonable simulation time effort and the possibility to still extracting all necessary local simulation result information. Special attention has been given to the simulation sequence used for the proposed model. Because the embedding technology involves multiple temperature critical production process steps it is advised to transfer the residual stresses of the previous step into the following. This ensures simulation results with high quality. Furthermore it is proposed to update the geometries according to the process calculations. In this work a feasible modeling approach for the underfill curing process is given. With the proposed framework the structural behavior of an embedded IC component both during the manufacturing stage and under environmental loading conditions can be investigated. This will facilitate future design choices and help expose the reliability potential of the novel embedding technology compared to conventional SMT.