In the context of power electronic interfaces in photovoltaic (PV), fuel cell, battery, and microgrid applications, the low output voltage of the DC source necessitates a voltage-boosting inverter. This paper proposes a single-source seven-level switched-capacitor boost inverter, particularly for low-voltage applications. The proposed inverter has the capability to produce seven different output voltage levels, i.e., intermediate boosted levels, with a total gain of three times the input voltage. The inverter has the advantage of a reduced number of power switches, diodes, and a switched-capacitor unit, which allows for single-stage operation without the need for a second DC-DC converter. The operating principle of the proposed inverter is explained in detail with a complete switching state analysis, conduction path analysis, and output voltage generation. The capacitor size is calculated using a charge balance-based equation. The self-balancing capability is validated for mismatched initial voltages with a bounded steady-state ripple. To evaluate the performance of the proposed inverter in a more realistic scenario, the effects of non-ideal device characteristics are considered, and the efficiency of the inverter is estimated using a loss model. A predictive current control technique is applied to control the output current under inductive load conditions. The simulation results obtained in MATLAB/Simulink software validate the proper seven-level operation of the inverter, the self-balancing capability of the capacitors, improved output waveform quality, and current control. The proposed inverter can be extended to grid-connected applications, where conventional output filters can be applied to meet the harmonic standards.

In Part 1 of this work, we have devised the electrostatics and the dc current model of AlGaAs/GaAs high-mobility field-effect transistor (HEMT). In Part 2, the terminal charges, potential, electric field, and short-channel effects within the channel are worked out. Despite its accuracy, this HEMT model retains the simplicity of industry-standard transistor models. We demonstrate that it can also be formulated to ensure compatibility with the Penn State Philips (PSP) model.

This paper presents an analysis of digitally based analog amplifiers (DB-OTAs). The operating principle and the main mathematical relations of digitally based differential amplifiers are discussed along with an explanation of its operating regions and of the corresponding power consumption.

The design and the silicon characterization of two mostly digital, low-voltage, energy- and area-efficient Relaxation Digital-to-Analog Converters (ReDACs) in 180 nm featuring digital self-calibration and parasitics-induced error suppression are presented and compared in this paper. The first design is a single-ended ReDAC (SE-ReDAC) and operates at 880 kS/s with a 10-bit resolution, while the second is based on a differential ReDAC (Diff-ReDAC) architecture and operates at 100 kS/s with a 13-bit resolution. The SE-ReDAC testchip in 180nm occupies just 5,030 μm 2 and operates with a supply voltage ranging from 0.6V to 1V. Experimental results at 0.65V reveal a 72.18 dB-SFDR, a 65.59 dB-THD and a 56.09 dB SINAD, resulting in 9.02 ENOB, with a power dissipation of just 3.3μW, achieving a competitive energy-efficiency (area-normalized energy efficiency) figure of merit FOM (FOM A ) of 166 dB (175 dB). On the other hand, the 180-nm Diff-ReDAC testchip occupies 7,800 μm 2 and operates in a supply voltage range from 0.45V to 1V, while achieving a 77.81 dB-SFDR, a 77.52 dB-THD and a 65.82 dB-SINAD (10.64 ENOB) at 0.6V supply with a power consumption of just 880nW, leading to a very competitive FOM (FOM A ) of 172 dB (178 dB).

In this paper, a two-stage inverter-based operational transconductance amplifier (OTA) is presented and investigated in terms of Electromagnetic Interference (EMI) susceptibility, by comparing it against the well-investigated topology of the twostage Miller OTA. Post-layout simulations demonstrate higher EMI immunity for the inverter-based amplifier by approximately one order of magnitude, due to their simple and symmetric circuital topology without current mirrors, differential pairs and current biasing.

We introduce a compact core model for double-gate (DGFET) and surrounding-gate (SGFET) MOSFETs designed for circuit simulations. Despite its high precision, the model is crafted to retain the same analytic formulation of the industry standard Pennsylvania State and Philips (PSP). Instead of linearizing the drain current as in the PSP model, we employ a quadratic symmetric polynomial interpolation of the charge in the channel. This eliminates the need for cumbersome derivatives, simplifications, and intricate coding when integrating into a circuit simulator, thereby preventing singularities during numerical iterations. Moreover, thanks to its mathematical formulation equivalent to PSP, this model simplifies the coding of terminal charges, capacitances, potentials, and electric fields in the channel within circuit simulators. We validate the accuracy of the model through comparisons with numerical solutions and experiments from the literature.

OBJECTIVE:Color Adjustment Potential evaluates the color blending of dental Composite Resins. While Color Adjustment Potential is simple, its clinical relevance is unclear. This research aims to understand it better and to create an index for Composite Resins with meaningful clinical interpretation. MATERIALS AND METHODS:Single and double shade composite disks of various diameters and opacities were created to test the indices. Color measurements used a dental colorimeter, avoiding subjective assessments. Color Adjustment Potential analysis of each material revealed insights, leading to the creation of a new Color Blending Threshold, providing a clinically relevant numerical value for Composite Resins. RESULTS:Color Adjustment Potential's numerical significance was clarified and introduced a new index for clinical applications. Color adaptation of each test shade to all Vita shades was also calculated, useful for single-shade restorations in open and closed cavity types. CONCLUSIONS:The proposed Color Blending Threshold defines the open/closed cavity dimension that can be adequately restored with a single shade of resin composite. CLINICAL SIGNIFICANCE:Understanding how dental materials adapt to surrounding tooth colors enhances esthetic restorations, simplifies shade matching, and optimizes resin composite production. The proposed Color Blending Threshold is a parameter that directly relates to the clinical significance of a material's true color blending ability. It defines the cavity dimension that can be adequately restored with a single shade of resin composite while ensuring that the resulting color difference falls below a predetermined threshold, meeting the clinical requirements for an esthetic restoration.

This study thoroughly compares multiple single bidirectional and multiport converters (MPCs), highlighting the significant role of MPCs in multi-input and multi-output (MIMO) systems. MPCs offer a more efficient and cost-effective solution than multiple single converters, especially in applications involving photovoltaic (PV), electric vehicles (EVs) with storage systems, and power grids. This research emphasizes the importance of multi-input converters (MICs) in integrating diverse voltage sources. It notes the rising popularity of multi-output DC-DC converters in portable electronics, owing to their reduced component count, lower costs, and compact design. This paper emphasizes comparisons based on diverse aspects and applications, shedding light on recent developments in basic bidirectional converters. Additionally, it delves into the advancements in MPC topologies, focusing on efficiency, reliability, and modularity improvements. These advancements are crucial for harnessing cost reduction, simplicity, and compactness. Furthermore, this paper introduces an innovative multiport DC-DC converter tailored for integrating and managing renewable sources. This new converter design enhances PV system and battery storage performance by reducing power conversion steps, using fewer components, and improving voltage-boosting capabilities. Its unique bidirectional buck-boost structure allows for versatile connections between sources and loads with varying voltage and power requirements. The performance of this novel converter is evaluated through MATLAB/Simulink simulations under different scenarios. Experimental studies further validate its effectiveness, marking a significant contribution to power conversion and management in integrating renewable sources such as DC microgrids.

This paper investigates the effect of Electromagnetic Interferences (EMI) on inverter-based analog amplifiers, as the Nauta operational transconductance amplifier (OTA). We show that, thanks to the their simple circuital topology that does not include current mirrors and differential pair, the inverter-based analog amplifiers have a much higher EMI immunity respect to the classical topologies: about one order of magnitude.

A novel ultra-low power amplifier is presented, composed of a Nauta amplifier (1 st stage) and a digital OTA (2 nd stage). This configuration significantly improves the performance in terms of signal distortion, by allowing the DIGOTA to work in a better operating window. The proposed amplifier has been a validated through simulations in TSMC $0.18\ \mu \mathrm{m}$ and compared to the DIGOTA: when used as a voltage-follower it features a much lower output distortion, especially for low amplitude signals.

This article presents the effects of electromagnetic interferences in common instrumentation, like multimeters and oscilloscopes. This investigation is of paramount importance when the interferences can directly reach the instrumentation used to verify the susceptibility of the circuits under test. In particular, the referred case of study is that of electromagnetic interferences injected through the ground plane into the output terminals of the analog integrated circuits. The measurements show that the susceptibility of the instrumentation depends on the amplitude, the coupling, and the frequency, but generally it remains low and mostly negligible.

This paper presents a new core compact model of double-gate (DGFET) and surrounding-gate (SGFET) MOSFETs for circuit simulations. The current and the terminal charges are continuous with high computation efficiency and accuracy. Despite its accuracy, it retains the same simplicity of the industry standard transistors models. The drain current is worked out without invoking the charge-sheet approximation exploiting a quadratic symmetric polynomial interpolation of the charge in the channel. Apart this clear approximation, no other simplification is used to work out the drain current, the terminal charges, the potential, and electric field in the channel. The accuracy of the model is shown by comparison with the exact numerical solution and experimental data of the literature.

This paper presents a digital intensive, compact and energy efficient 13-bit, 100-kS/s Differential Relaxation Digital to Analog converter (Diff-ReDAC) in 180 nm CMOS. The DiffReDAC is able to operate in a supply voltage range from 0.45 V to 1 V having power consumption ranging from 420 nW to 2,650 nW. It has an area footprint of only 7,800$\mu \mathrm{m}^{2}$ while achieving, at 0. 6V a maximum INL (DNL) of 1. 07LSB(0.96LSB), 77. 81dB(77.52dB) of SFDR (THD) and 65. 82dB SINAD, resulting in 10. 64ENOB. Its low power dissipation of 880nW results in extremely competitive energy efficiency (area-normalzed energy efficiency) figures of merits FOM (FO$\mathrm{M}_{\mathrm{A}}$) of 172 dB(178dB).

Digital-based differential amplifiers (DDA) are particularly suitable to low voltage digital integrated circuit technologies. This paper presents an exhaustive analysis of digital-based analog amplifiers to take advantage of today’s high-performance digital technologies, and of computer aided design (CAD), which is commonly employed to design integrated circuits. The operating principle and the main mathematical relations of digital-based differential amplifiers are discussed along with an exhaustive explanation of its operating regions and of the corresponding power consumption. These aspects, which are not discussed in the literature, are very important for the circuit designers. Finally, a detailed description of the design procedure of the UMC 180nm standard CMOS technology is provided.

In this article, we show a simple power device architecture that combines the features of the SIT and the power MOSFET: insulated gate, positive threshold, fast switching, current deep in the semiconductor, and compact design. It has the conduction characteristics of a BSIT, and it is voltage-controlled as a MOSFET. Since the large part of the current is not confined at the semiconductor/insulator interface, we believe that it is a promising structure to take advantage of wide bandgap semiconductors that, despite the high mobility and breakdown voltage, still lack high-quality oxide–semiconductor interfaces. The device architecture is devised by means of device simulation both in static and dynamic conditions.

Multi-level inverters (MLIs) have been widely used in recent years due to their various advantages in industrial and grid-connected applications. Traditional MLI topologies are being hampered by the rapid surge of renewable energy systems (RES) as a result of performance difficulties such as poor power reliability, an economically unviable structure, and a lack of efficiency. These difficulties are due to the traditional MLI topologies' inability to keep up with the increasing demand for RES. Because of concerns about performance and limitations posed by classic MLI topologies, researchers have found themselves driven to the idea of building innovative hybrid MLI topologies. This study provides a comprehensive analysis of multilevel inverter systems that are wired into the main power supply. Grid-connected inverter types and their configurations are discussed in depth in this review. Diverse multi-level inverter topologies, as well as the different approaches, are divided into various categories and discussed in depth. Additionally, a number of control reference frames for inverters were brought forward for discussion. Furthermore, different inverter control strategies were investigated, followed by a tabular summary of recent developments in the inverter-related literature for the convenience of the readers. Moreover, the recently proposed grid-connected multi-level inverter systems were discussed including their findings and innovations. In conclusion, a brief description of the study's scope was offered and research directions for future studies were provided.

A reconfigurable, high-impedance, DC-coupled low-frequency digital acquisition front-end (DAFE) suitable to operate under a power supply voltage ranging from 0.2 to IV down to 600 pW power is presented in this paper. Matching-indifferent DC accuracy over a rail-to-rail input range is uniquely achieved by the new time-multiplexed digital differential amplification technique at ultra-low area and without chopping and auto-zeroing. A 180 nm testchip of the proposed DAFE occupies 0.00945 mm 2 and draws 4.5 nW at a 0.4 V supply, has a 120 Hz gain-bandwidth product, with an in-band input noise of 11.3 µV r ms , a 137 µV input offset voltage standard deviation, 65.7dB CMRR, 63.8dB PSRR, and provides a 46.5dB-SFDR, 6.9 bit-ENOB digitized output at -12 dBFS.

This paper proposes an improved topology of the three-phase series resonant DC-DC Boost converter with variable frequency control. The DC output voltage can be properly regulated at a constant value from no-load condition to full-load condition by adjusting the switching frequency. This is feasible with the three series resonant circuits coupled to the three-phase inverter. The leakage and mutual inductances of the step-up transformer are used implicitly in the series resonant circuits. Therefore, the proposed converter, when matched to the traditional three-phase inter-leaved LLC converters, requires fewer transformers, passive components, and switching devices. Furthermore, it offers better efficiency and size reduction. The proposed SRC converter also relies on the transformer’s magnetizing inductance to ensure zero voltage switching (ZVS) for all the switches within the considered range of the operating frequency. The deployed variable frequency controller shows a good level of stability at the considered loading conditions. The output voltage-to-input voltage ratio is steadily regulated at 6:1, irrespective of the load variation, by varying the switching frequency. The experimental validation of the theoretical findings proceeded on a low power scaled-down laboratory prototype. From the achieved results, the performance of the proposed converter (in terms of its effectiveness) was validated.

This paper presents a voltage-controlled delay unit (VCDU) with a novel architecture allowing for a wide input range of linearity and an improved immunity to electromagnetic interferences. The circuit is based on a current-starved inverter with a biasing technique to extend the input voltage range of linearity near to the rail-to-rail linearity range. The proposed scheme was designed by UMC 180 nm standard CMOS process and works without power-hungry amplifiers or comparators. It has a voltage supply of 1.8 V and exhibits a rail-to-rail linearity range (0–1.8 V) with an average EMI-induced jitter of only 1% of the nominal delay.

With the maturity of CMOS technologies and their use in low-voltage analog applications, the accuracy of SPICE models is very important. Here, an extremely accurate yet simple form of the charge-sheet model is developed using a symmetric polynomial interpolation of the charge in the channel. This formulation of the drain current retains the same simplicity of the industry-standard surface potential MOSFET models based on the symmetric linearization method (SLM). But, unlike the SLM, it is developed without requiring the linearization of the charge in the channel, hence, the asymmetries and the nonlinearity are accurately accounted for. The model, although more accurate, has the same computational efficiency and easy implementation of the SLM. Finally, the equations of the currents and terminal charges can be worked out to have the same mathematical form as the SLM.