Exploiting at best every bit of memory on chip is a must for finding the best trade-off between cost and performance when designing Many-Core MPSoCs. In this paper, we propose a new memory hierarchy organization that maximizes the usage of the available memory at each cache level while avoiding data redundancy. We also aim to reduce data access time by avoiding data migration. Our scheme is based on Non-Uniform Cache Architectures (NUCA), and makes use of a novel NoC multicast messaging support. It requires to logically partition the network into imagined layers in which each layer is bound to one of the cache levels. We assess the efficiency of our proposal by evaluating performance metrics, using the Gem5 simulator and the Splash2 benchmark suite. Our results show an improvement of 24% in L2 miss rate over baseline S_NUCA organization and more than 25% in average network latency. We report a maximum improvement of 40% in execution time. Also, we show that our approach outperforms R_NUCA.

Future many cores, either for high performance computing or for embedded applications, are facing the power wall, and cannot be scaled up using only the reduction of technology nodes; 3D integration, using through silicon via (TSV) as an advanced packaging technology, allows further system integration, while reducing the power dissipation devoted to system-level communication. In this paper, we present a 3D modular and scalable network-on-chip (NoC) architecture implemented using robust asynchronous logic. The 3DNOC circuit targets a Telecom long-term evolution application; it is composed of two die layers, fabricated in 65 nm technology using TSV middle aspect ratio 1: 8, and integrates ESD protection, a 3D design-for-test, and a fault tolerant scheme. The 3D links achieve 0.66 pJ/b energy consumption and 326 Mb/s data rate per pin for the parallel link. Thin die effect is demonstrated by thermal analysis and measurements, as well as the dynamic self-adaptation of the 3D link performances with 3D thermal conditions. Finally, the scalability of the 3DNOC circuit, in terms of power delivery network and thermal dissipation, is demonstrated by using simulations up to a 3D stack of eight die layers.

This paper addresses elevator assignment in vertically-partially-connected 3-D-networks-on-chip (NoCs). Elevators are vertical links between dies. Because of yield issues, Through-Silicon-Via (TSV) cost, and heterogeneity in dimension, topology, and technology of different dies, vertically-partially-connected topologies seem unavoidable in the emerging 3-D-NoCs as opposed to fully-connected topologies. In such partially-connected topologies, as there are fewer elevators than routers, the assignment of elevators to routers becomes a new 3-D-specific optimization problem. An improper assignment can lead to dramatic network performance degradation. This paper proposes an elevator assignment method for best-effort wormhole 3-D-NoCs to improve the average network performance. Experimental results show an improvement of about 90% even compared to a greedy (intrinsically good) initial assignment.

In this paper, we propose a distributed routing algorithm for vertically partially connected regular 2D topologies of different shapes and sizes (e.g., 2D mesh, torus, ring). The topologies that are the target of this algorithm are of practical interest in the 3D integration of heterogeneous dies using Through-Silicon-Vias (TSVs). Indeed, TSV-based 3D integration allows to envision the stacking of dies with different functions and technologies, using as an interconnect backbone a 3D-NoC. Intrinsically, 3D topologies have better performances, but yield and active area (and thus the cost) are function of the number of TSVs; therefore, the designs tend to use only a subset of available TSVs between two dies. The definition of blockage free and low implementation cost distributed deterministic routing on this kind of topology is thus of theoretical and practical interests. We formally prove that independently of the shape and dimensions of the planar topologies and of the number and placement of the TSVs, the proposed routing algorithm using two virtual channels in the plane is deadlock and livelock free. We also experimentally show that the performance of this algorithm is still acceptable when the number of vertical connections decreases.

In this paper, we detail the design and implementation of a router for vertically-partially-connected 3D-NoCs based on stacked 2D-meshes. This router implements the necessary hardware to support a recently introduced routing algorithm called "Elevator-First", which targets topologies with irregularly placed vertical connections in a deadlock free manner, using only two virtual channels in the plane. The micro-architectural design shows that the proposed router requires few additional hardware. Our studies about the practicality of the algorithm and its router implementation demonstrate that it has low overhead compared to a router for fully connected 3D-NoCs. Using ST Microelectronics 65nm CMOS technology Elevator-First router with 7 ports has a total area of 0.07mm2, an Operating frequency of over 3GHz and a power consumption of around 3mW.

This paper addresses link-buffer capacity allocation in the design process of best-effort 3DNoCs holding hotspot memory ports. We show that in 3DSoCs with integrated wide I/O DRAMs, the congestion spreading is different from SoCs with external DRAMs: the bottlenecks are not anymore the external memory ports but the network links that become saturated and retropropagate the congestion. The distribution of bottleneck links is directly affected by the traffic directed to the hot memory ports. Using an analytical performance evaluation method, we determine network link buffer capacities according to the given workload composed of regular and hotspot traffics.

This paper details the design and implementation of an asynchronous 3D-NoC router using a novel serialization scheme in the vertical directions which targets 3D production oriented processes. A study of the router cost has been conducted for medium and high density TSVs on 65nm and 32nm nodes. A router integrating the serial link has been implemented in 65nm using medium density TSVs. The serial link provides a throughput of 16 Gb/s for an area gain of 57%, and an additional cost of one NoC routing hop in latency and in energy.

The shrinking of processing technology in the deep submicron domain aggravates the imbalance between gate delays and wire delays. While a Network-on-Chip systematically tackles this physical issue by differentiating between local and global interconnects, 3D-Integration by folding the die into multiple layers and using short vertical links instead of long horizontal interconnects, leads to a considerable reduction in the length and the number of long global wires. This chapter elaborates on the strategic exploitation of these two key technologies, where the use of the third dimension in the design of the integrated networks provides a major improvement in the network performance. It makes a case for using asynchronous circuits to implement 3D-NoCs. We claim that asynchronous logic allows benefiting from serialized vertical link leading to the definition of innovative architectures which can address some critical issues of 3D integrated circuits using Through-Silicon-Vias. This allows complying with the cost-efficiency trade-off of the 3D-Integration paradigm.

This book presents the research challenges that are due to the introduction of the 3rd dimension in chips for researchers and covers the whole architectural design approach for 3D-SoCs. Nowadays the 3D-Integration technologies, 3D-Design techniques, and 3D-Architectures are emerging as interesting, truly hot, broad topics. The present book gathers the recent advances in the whole domain by renowned experts in the field to build a comprehensive and consistent book around the hot topics of three-dimensional architectures and micro-architectures. This book includes contributions from high level international teams working in this field.

Networks on chips constitute a new design paradigm for communication infrastructures in large multiprocessor SoCs. NoCs can use the GALS technique to address the difficulty of distributing a synchronous clock signal on the entire chip area. This article describes two approaches to implementing a distributed NoC in a GALS environment.

In this paper we present a systematic comparison between two different implementations of a distributed Network on Chip: fully asynchronous and multi-synchronous. The NoC architecture has been designed to be used in a Globally Asynchronous Locally Synchronous clusterized Multi Processors System on Chip. The 5 relevant parameters are Silicon Area, Network, Saturation Threshold, Communication Throughput, Packet Latency and Power Consumption. Both architectures have been physically implemented and simulated by SystemC/VHDL co-simulation. The electrical parameters have also been evaluated by post layout SPICE simulation for a 90nm CMOS fabrication process, taking into account the long wire effects.

This paper presents three high-throughput low-latency FIFOs that can be used as efficient and reliable interfaces between different domains in hybrid-timing systems. These three hardware components have been designed to be used in a Globally Asynchronous Locally Synchronous clusterized Multi-Processor System-on-Chip communicating by a Multi-Synchronous or by a fully Asynchronous Network-on-Chip. The proposed architectures are rather generic and allow the system designer to make various trade-off between latency and robustness, depending on selected synchronizer. These FIFOs have been physically implemented with portable ALLIANCE CMOS standard cell library and the architectures have been evaluated by SPICE simulation for a 90nm CMOS fabrication process.

This paper presents two high-throughput, low-latency converters that can be used to convert synchronous communication protocol to asynchronous one and vice versa. These two hardware components have been designed to be used in Multi-Processor System on Chip respecting the GALS (Globally Asynchronous Locally Synchronous) paradigm and communicating by a fully asynchronous Network on Chip (NoC). The proposed architecture is rather generic, and allows the system designer to make various trade-off between latency and robustness, depending on the selected synchronizer. These converters have been physically implemented with the portable ALLIANCE CMOS standard cell library and the architecture has been evaluated by SPICE simulation for a 90nm CMOS fabrication process.

Ce papier presente le micro-reseau DSPIN qui est une evolution de l'architecture SPIN. DSPIN est un micro-reseau a commutation de paquets pour architectures multiprocesseurs integres sur puce (MPSoC) utilisant l'approche GALS (Globalement Asynchrone, Localement Synchrone). L'architecture de DSPIN a une surface de silicium tres petite et fournit des canaux de communication avec garanties de latence et de bande passante pour des applications soumises a des contraintes temps-reel.

The paper presents the DSPIN micro-network, that is an evolution of the SPIN architecture. DSPIN is a scalable packet switching micro-network dedicated to GALS (globally asynchronous, locally synchronous) clustered, multi-processors, systems on chip. The DSPIN architecture has a very small footprint and provides to the system designer both guaranteed latency, and guaranteed throughput services for real-time applications