We model experimental NanoWire (NW) nFET I-V aging under Bias Temperature Instability (BTI) and Hot-Carrier (HC) stress using our compact physics-aware framework ComphU. We introduce a new simplified and computationally efficient approach to Distribution Function (DF) modeling applicable for short- $L_{\mathrm{g}}$ FETs and successfully lump the time- 0 variability into a limited parameter set. Our model describes experimental $\Delta V_{\text {th }}(t)$ and $\Delta I_{\text {d,on }}(t)$ traces well. Using the calibrated model, we find that $i$) the intrinsic time- $0 g_{m, \text { max }}$ is 39 % higher than the extrinsic one, ii) aging outside the calibration region is predicted reasonably, and that the BTI lifetime iii) roughly doubles for every 0.1 V reduction in the supply voltage and $i v$) increases up to $6.3 \times$ for every 0.1 V increase in $V_{\text {th, } 0}$.

We present imecSHE, a 3-D deterministic Boltzmann transport equation (BTE) solver for computing heat generation in realistic devices. Input-power-scaled Gaussian heat-generation profiles are shown to overestimate heating in the nanosheet-FET (NSFET) by an order of magnitude. Our simulations resolve the 3-D topology of heat generation and show that lowering the carrier effective mass can significantly reduce heating. Mobility-inferred effective mass is further employed to qualitatively study the channel reorientation effect on heat generation. Along the imec roadmap A14 -> A3 scaling, p-FETs benefit the most with the heat-fraction (HF) dropping from 0.76% to 0.32%, while the n-FET HF is nearly unchanged. Finally, scaling studies identify actionable levers. Shorter channels and smaller drain size reduce heat. By providing physics-based heat-generation profiles in realistic 3-D devices instead of assumed heat sources, imecSHE enables quantitative optimization of device and process design to suppress heat generation for technology pathfinding.

We propose an extended version of the design technology co-optimization (DTCO) flow, which-in contrast to the commonly acknowledged DTCO paradigm relying on the power-performance-area (PPA) metric-considers reliability as a tangible parameter, thereby leading to a concept of PPAR ("R" stands for "reliability"). As a demonstration of this concept, we carry out a comprehensive reliability analysis of future imec nanosheet field-effect-transistor (NSFET) logic nodes with gate lengths scaling from 15 to 10 nm. Our focus is placed on hot-carrier degradation (HCD) and bias temperature instability (BTI) modeling over stress time of up to ten years. For an accurate description of HCD, we employ our technology computer-aided design (TCAD)-based HCD model, which relies on the modeling of carrier transport. A thorough analysis of the electric field and carrier concentration shows that both quantities peak at the rounded nanosheet (NS) corners, which enhances HCD; the most severe HCD occurs in NSFETs with the smallest corner radii. BTI simulations-conducted with the nonradiative multiphonon (NMP) model-exhibit a similar behavior: BTI becomes stronger as the NS corners become sharper. Overall, all degradation metrics decrease monotonically as the NS corner radius increases. These results indicate that field-effect transistor (FET) architectures with larger NS corner radii provide improved robustness against both HCD and BTI, and should be favored for future technology nodes. Our concept allows considering the reliability of future (not yet fabricated) transistor nodes, thereby making reliability an essential DTCO ingredient.

We apply our finite element-based framework, introduced in Part 1, to understand the effects of channel thickness and doping on the degradation of indium-gallium-zinc oxide (IGZO)-based thin-film transistors (TFTs) with different architectures. By taking into account only experimentally extracted band alignments and amorphous semiconductor-specific physics, it is possible to explain apparent discrepancies in previously reported positive bias temperature instabilities (PBTI) trends. Our analysis shows that common PBTI benchmarks used in standard inversion-mode bulk Si devices cannot be employed in thin-film accumulation-mode IGZO devices. Finally, based on these insights, we propose device optimization strategies to reduce the electron trapping component of PBTI in amorphous IGZO TFTs.

Integrating In-Ga-Zn oxide (IGZO) channel transistors into silicon-based ecosystems requires the resilience of the channel material to hydrogen. Standard In-rich IGZO (In = 40 metal at. %) suffers from degradation under forming gas anneal (FGA) and hydrogen-driven positive bias temperature instability (PBTI). In this paper, we demonstrate scaled, top-gated transistors with an atomic layer deposition (ALD)-deposited In-poor (In <= 17 metal atom %) IGZO channel that shows superior resilience to hydrogen compared to those with an In-rich IGZO channel. These devices, fabricated with a 300 mm semiconductor fabrication plant (FAB) process, with dimensions down to W CH x L TG = 80 x 40 nm2, show excellent stability during a 2 h, 420 degrees C forming gas anneal (0.06 <= |Delta V TH| <= 0.33 V) and improved resilience to H in PBTI at 125 degrees C (down to no detectable H-induced V TH shift) compared to In-rich devices. We demonstrate that the mechanism of device degradation by H in the FGA is different from that of the H-induced V TH instability in PBTI. We argue that the first is due to oxygen scavenging by H, and the second, H release from the gate dielectric into the channel. We also show that resilience to H in one process does not automatically translate to resilience to H in the other. This significant improvement in IGZO resilience to H enables the use of FGA treatments during fabrication, needed for silicon technology compatibility, as well as further scaling and 3D integration, bringing IGZO-based technologies closer to mass production.

The tremendous surge in the interest in oxide semiconductors for applications such as Flash memories, 3D DRAM, RF circuits, displays, flexible electronics, is driven by the advantages of these materials over conventional choices [1]. Their CMOS back end of line (BEOL) compatibility helps enable novel complex functionalities without an overhead in the footprint. Additionally, these large band gap materials give an ultra-low off-current for reduced standby power. The application spectrum is growing, and multiple control knobs provide a large design space. Understanding of the device fundamentals, stack engineering and processing, and reliability assessment and modeling are vital to achieve the specifications for the targeted applications. Here, we focus on thin film transistors (TFTs) and use In-Ga-Zn-O (IGZO) as a representative material to discuss the different aspects. These device design and assessment guidelines can be extended to other oxide semiconductors.

Reliability in IGZO thin-film transistors (TFT) is known to be limited by Bias Temperature Instability (BTI), however there are no detailed studies on other reliability mechanisms, like dielectric breakdown. We study both bottom-gated and top-gated transistors and find different area scaling trends in those devices, which could be partially explained with a non-uniform voltage distribution across the active area during the voltage accelerated breakdown stress. Both bottom and top-gated TFT obtain a maximum tolerable voltage of more than 2V at 95 degrees C for 10 years. Even for the smallest measured device, 80x25nm(2), breakdown is not a reliability concern.

While we demonstrate a back-gated (BG) amorphous Indium-Gallium-Zinc-Oxide (a-IGZO) transistors with a nearly ideal subthreshold slope (SS) ~ 60 mV/dec. However, SS degrades when a top-gated (TG) configuration is implemented. The energy distribution of traps inferred from temperature-dependent (T = 4 K - 300 K) and multi-frequency (f = 1 kHz - 100 kHz) admittance measurements, reveals a much higher trap density in TG devices. By analyzing the impact of each process step and conducting forming gas anneal (FGA) experiments, we reveal the role of hydrogen in the deterioration of the SS in the IGZO-based transistors.

Thin-film transistors based on amorphous oxide semiconductors (AOS) are promising candidates for enabling further DRAM scaling and 3D integration, which are critical for advanced computing. Despite extensive research, the charge transport mechanism in these disordered semiconductors remains poorly understood. In this work, we investigate charge transport in the archetypical AOS material, indium gallium zinc oxide (IGZO), across a range of compositions and temperatures using thin-film transistors and Hall bar structures. Our results show that the electrons involved in transport exhibit partially spatial coherence and non-degenerate conduction. Under these conditions, transport is dominated by electron transfer across insulating gaps between locally coherent regions, rather than by degenerate percolative transport above a mobility edge, or by localized-state hopping, both of which are widely assumed in the literature. While fluctuation-induced tunnelling has previously been invoked to describe low-temperature transport in oxide transistors, we show that such behavior originates from partially coherent electronic states and develop a field-effect-aware fluctuation-induced tunnelling (FEAFIT) framework that explicitly accounts for gate modulation of the tunneling landscape. The FEAFIT model accurately predicts experimental data across all compositions, temperatures, and gate voltages, enabling extraction of fundamental transport parameters. These tunnelling parameters are then correlated with electron coherence dimensions and the degree of energetic disorder obtained from first-principles calculations. Our findings advance the fundamental understanding of charge transport in AOS-based transistors and provide a foundation for further performance improvements

We extend our compact physics model (CPM) for hot-carrier degradation (HCD) to cover the impact of ambient temperature on HCD. Three components of this impact are taken into account. First, variations in temperature perturb carrier transport. Second, the thermal component of Si-H bond rupture becomes more prominent at elevated temperatures. Third, vibrational lifetime of the bond decreases with temperature. While the first and the third mechanisms impede HCD, the second one accelerates this detrimental phenomenon. The aforementioned mechanisms are consolidated in our extended CPM, which was verified against experimental data acquired from foundry quality n-channel transistors with a gate length of 28 nm. For model validation, we use experimental data recorded using four combinations of gate and drain voltages and across a broad temperature range of 150–300 K. We demonstrate that the extended CPM is capable of reproducing measured degradation ΔId,lin(t) (normalized change of the linear drain current with stress time) traces with good accuracy over a broad temperature range.

Amorphous indium gallium zinc oxide (a-IGZO) is becoming an increasingly important technological material. Transport in this material is conceptualized as the heavy disorder of the material causing a conduction or mobility band-edge that randomly varies and undulates in space across the entire system. Thus, transport is envisioned as being dominated by percolation physics as carriers traverse this varying band-edge landscape of “hills” and “valleys”. It is then something of a missed opportunity to model such a system using only a compact approach—despite this being the primary focus of the existing literature—as such a system can easily be faithfully reproduced as a true microscopic TCAD model with a real physically varying potential. Thus, in this work, we develop such a “microscopic” TCAD model of a-IGZO and detail a number of key aspects of its implementation. We then demonstrate that it can accurately reproduce experimental results and consider the issue of the addition of non-conducting band-tail states in a numerically efficient manner. Finally, two short studies of 3D effects are undertaken to illustrate the utility of the model: specifically, the cases of variation effects as a function of device size and as a function of surface roughness scattering.

For operation as power amplifiers in RF applications, high electron mobility transistor (HEMT) structures are subjected to a range of bias conditions, applied at both the gate and drain terminals, as the device is biased from the OFF- to ON-state conditions. The stability of the device threshold voltage (Vt) condition is imperative from a circuit-design perspective and is the focus of this study, where stresses in both the ON and OFF states are explored. We see rapid positive threshold voltage increases under negative bias stress and subsequent recovery (i.e., Vt reduces), whereas conversely, we see a negative Vt shift under positive stress and Vt increase during the subsequent relaxation phase. These effects are correlated with the thickness of the GaN layer and ultimately result from the deep carbon-acceptor levels in the C-GaN back barrier incorporated to screen the buffer between the silicon substrate and the epitaxially grown GaN layer. Methods to mitigate this effect are explored, and the consequences are discussed.

Ferroelectricity boosted gate stacks, such as dual ferroelectric layer and charge trap layer (dual FE-CTL), have been proposed and confirmed to lead to improvements in program performance. However, the detailed analysis of reliability on the devices has not been sufficiently investigated to date. In this work, short time data retention and program/erase cycling endurance on dual FE-CTL gate stacks are investigated by fast I-V. The results reveal significant advantages of dual FE-CTL gate stacks in memory reliability. In addition, lower transient gate current during program is observed, which is related to the improvements on dual FE-CTL gate stacks.

We perform trap density (Dt) extraction through admittance measurements on amorphous Indium-Gallium-Zinc-Oxide (a-IGZO) thin films using multi-finger MOS structures. We investigate the impact of channel length (Lch) on C-V and G-V characteristics and demonstrate a reliable trap density extraction method in short channel devices. The method is validated for pure and Magnesium-doped a-IGZO (Mg:IGZO). The experimental results are consistent with simulations based on a distributed network model.

This paper addresses the correct analysis of electrical data from devices with gate oxides 20 nm that mimic those used in high voltage periphery devices of 3D NAND flash. Thick oxides grown on an active-Si region surrounded by shallow trench isolation are found to be thinner at the side and corner regions leading to contradictory electrical observations. We introduce a model where the gate oxide is divided into three different regions with different equivalent oxide thicknesses. This provides a simple way to explain the apparently conflicting electrical data and emphasizes the role of side and corner oxide regions in leakage and breakdown. By applying the model to different oxide growth processes, we also provide guidelines to limit oxide thickness variations.

We report on charge capture and emission in Metal-Oxide-Semiconductor AlGaN/AlN/GaN High-Electron Mobility Transistors (MOS-HEMT) foreseen as power amplifiers in mm-wave user-equipment operating at RF frequencies. These devices target Enhancement mode operation, necessitating the incorporation of high-permittivity (high-kappa) dielectrics to mitigate barrier thinning induced leakage. It is shown that defects in the bulk of HfO2 or Al2O3 dielectrics result in significant V-t instabilities, with dielectric-dependent charge emission kinetics: band alignment between high-kappa shallow defect levels and AlGaN conduction band enables full (Al2O3) or partial (HfO2) charge detrapping, while a deeper level in HfO2 enables trapping even at threshold conditions. The significance of this work lies in revealing the degradation modes present under DC which can also contribute at RF operating conditions.

We study the role of oxygen flow during IGZO PVD process on the high temperature PBTI mechanisms in back-gated TFTs by combining light-assisted with electrical stress measurements. The oxygen flow is observed to affect the magnitude of the charge trapping component (positive Delta V-th) and hydrogen related progressive channel doping mechanism (negative Delta V-th) during PBTI stress. By exploiting light-induced de-trapping from IGZO deep states we show a direct correlation between deep sub-gap DOS and the oxygen flow during IGZO deposition: the larger the oxygen flow, the smaller the light response at time-zero and its increase during PBTI stress, despite a larger negative Delta V-th. We ascribe the light-response to metalmetal complexes which can be passivated by oxygen.

Negative bias temperature instability (NBTI) of IGZO thin film transistors (TFTs) with different channel thicknesses(tIGZO) and gate lengths is studied. Four main NBTI characteristics are observed: (1) the threshold voltage shift appears to be almost independent of the gate stress voltage (above a given stress voltage determined by the tIGZO), and shows (2) a large activation energy (i.e., a strong temperature dependence) and (3) a steep time kinetics (i.e., a large power-law time exponent), while (4) the NBTI relaxation rate is reduced for increasing temperatures below 200°C. By combining TCAD simulations with experimental data modelling, these peculiar features can be explained by an oxide-field-driven hydrogen release from the gate-dielectric, inducing additional IGZO donor doping and a subsequent negative $V_{\text{th}}$ shift. The latter mechanism is observed to be analogous to the negative $V_{th}$ shift reported during PBTI stress at elevated temperature in IGZO devices [1].

Total-ionizing-dose (TID) effects are evaluated in top-gated IGZO thin-film transistors (TFTs) irradiated with different gate biases. Negative-bias irradiation leads to worst case degradation of TID response, primarily due to enhanced charge trapping in the SiO2 insulator that underlies the IGZO channel and serves as an oxygen-penetration layer during device processing. TID response comparisons with back-gated devices indicate that hydrogen also plays an important role in the observed degradation of top-gated devices. The source of this hydrogen is most likely SiN oxygen blocking layers. Comparisons with other display and alternative-channel MOS technologies illustrate that further optimization should enable the use of IGZO in future space applications.