This study presents a Technology Computer Aided Design (TCAD) and comprehensive Design-Technology Co-Optimization (DTCO) approach to evaluate and enhance power and performance in Gate-All-Around Nanosheet (GAA-Nsh) and Forksheet (Fsh) architectures. The analysis focuses on the impact of active widths, sheet count, wall properties, and power delivery methods on the effective resistance (Reff) and capacitance (Ceff) of these devices. The research employs simulations of five-stage INVD1 ring oscillators (RO) at various metal pitches (Mx) to extract frequency and power data. Notably, a novel Gate-All-Around Forksheet (GAA-Fsh) structure is introduced, offering enhanced gate control while retaining the advantages of Fsh. The study also explores asymmetric N/PFETs within the Fsh technology, and innovative contacting approaches such as Buried Power Rail (BPR) and Backside Power Rail (BS-PR) with Backside Contact (BSC) to reduce access resistance. Results indicate that GAA-Fsh outperforms traditional GAA-Nsh and Fsh due to reduced Reff and Ceff, although it is process feasible only at larger Mx. At smaller Mx, GAA-Nsh demonstrates higher performance than Fsh at a given sheet width (Wsh), but Fsh, with the advantage of additional Wsh, can match GAA-Nsh performance at larger Wsh. Furthermore, the BPR and BS-PR contacting schemes are found to provide similar performance. This research provides valuable insights into future semiconductor device designs, emphasizing higher performance and efficient scaling.

Contacted-poly-pitch (CPP) scalability of gate-all-around (GAA) nanosheet (NS) device is investigated in detail. Combination of NS thickness (TNS) and junction abruptness (delta) allow for spacer thickness (T-SP) and gate-length (L-G) scaling. Contact-length L-CNT scaling does not affect intrinsic performance, but scaling is limited by middle-of-line and interface resistivity. Using an extensively calibrated advanced transport model combined with the transistor design-technology co-optimization (DTCO) flow we account for accurate device and circuit intrinsics and parasitics. We highlight the trade-off between T-SP and L-G scaling whereby L-G can be scaled more aggressively if T-SP can be relaxed. T-NS can be scaled to-3.5 nm maintaining iso-performance allowing for a minimum CPP of-38 nm at L-G 10 nm. Aggressively improving delta- can further allow CPP scaling to-34 nm (L-G similar to 6 nm), though T-NS scaling gain saturates due to severe transport degradation.

Contact-poly-pitch (CPP) scalability of Gate-All-Around-nanosheet (GAA-NS) device is investigated in detail in combination with sheet thickness (${T}_{\text{ns}}$) and junction abruptness ($\delta$) both allowing for spacer-thickness ($\mathbf{T}_{\mathbf{S P}}$) and gate-length ($\mathbf{L}_{\mathbf{G}}$) scaling. Using an extensively calibrated advanced transport model combining with the DTCO flow we account for accurate device and circuit intrinsics and parasitics. We highlight trade-off between Tsp and Lg scaling (Lg scaling better than Tsp); TNs can be scaled to $\boldsymbol{\sim} \mathbf{3. 5 n m}$ maintaining iso-performance allowing for a minimum CPP of $\sim 38 ~\text{nm}\left(L_{G} \sim 10 ~\text{nm}\right)$. Aggressively improving $\delta$ can further scale CPP to $\sim 34 ~\text{nm}\left(~{L}_{{G}} \sim 6 ~\text{nm}\right)$, though $\mathbf{T}_{\text {NS }}$ scaling gain saturates due to severe mobility degradation.

Thin-film transistors based on amorphous oxide semiconductors (AOS) are promising candidates for enabling further DRAM scaling and 3D integration, which are critical for advanced computing. Despite extensive research, the charge transport mechanism in these disordered semiconductors remains poorly understood. In this work, we investigate charge transport in the archetypical AOS material, indium gallium zinc oxide (IGZO), across a range of compositions and temperatures using thin-film transistors and Hall bar structures. Our results show that the electrons involved in transport exhibit partially spatial coherence and non-degenerate conduction. Under these conditions, transport is dominated by electron transfer across insulating gaps between locally coherent regions, rather than by degenerate percolative transport above a mobility edge, or by localized-state hopping, both of which are widely assumed in the literature. While fluctuation-induced tunnelling has previously been invoked to describe low-temperature transport in oxide transistors, we show that such behavior originates from partially coherent electronic states and develop a field-effect-aware fluctuation-induced tunnelling (FEAFIT) framework that explicitly accounts for gate modulation of the tunneling landscape. The FEAFIT model accurately predicts experimental data across all compositions, temperatures, and gate voltages, enabling extraction of fundamental transport parameters. These tunnelling parameters are then correlated with electron coherence dimensions and the degree of energetic disorder obtained from first-principles calculations. Our findings advance the fundamental understanding of charge transport in AOS-based transistors and provide a foundation for further performance improvements

Single-crystal SrTiO3 (STO) is an ultrahigh-κ insulator with an expected low interface trap density that promises high breakdown strength and has great potential to boost the reliability of two-dimensional (2D) field-effect transistors (FETs). Here we provide a detailed study of the performance, stability, and reliability of MoS2 FETs with STO gate insulators. Most importantly, we observe a small hysteresis for electric fields up to 8 MV cm-1 at a sweep rate range spanning 0.01-1 V s-1 and sweep times of kiloseconds. Interestingly, the hysteresis is counterclockwise and bias temperature instability (BTI) is often anomalous, both likely caused by the diffusion of oxygen vacancies. We also show that the hysteresis dynamics in MoS2/STO FETs are reproducible over a long time, which underlines their high reliability. Our findings show that STO is a promising gate insulator that might help overcome critical obstacles to highly reliable 2D nanoelectronics.

Amorphous indium gallium zinc oxide (a-IGZO) is becoming an increasingly important technological material. Transport in this material is conceptualized as the heavy disorder of the material causing a conduction or mobility band-edge that randomly varies and undulates in space across the entire system. Thus, transport is envisioned as being dominated by percolation physics as carriers traverse this varying band-edge landscape of “hills” and “valleys”. It is then something of a missed opportunity to model such a system using only a compact approach—despite this being the primary focus of the existing literature—as such a system can easily be faithfully reproduced as a true microscopic TCAD model with a real physically varying potential. Thus, in this work, we develop such a “microscopic” TCAD model of a-IGZO and detail a number of key aspects of its implementation. We then demonstrate that it can accurately reproduce experimental results and consider the issue of the addition of non-conducting band-tail states in a numerically efficient manner. Finally, two short studies of 3D effects are undertaken to illustrate the utility of the model: specifically, the cases of variation effects as a function of device size and as a function of surface roughness scattering.

Complimentary FETs (CFETs) enable aggressive standard cell height (CH) reduction, facilitating on-target area scaling without shrinking contacted gate pitch (CGP). We extensively benchmark nanosheet (NS) based CFETs against gate-all-around (GAA) NSFETs using power, performance, area (PPA) as well as scalability metrics. The impact of BEoL RC, new materials, DTCO boosters is further explored. 4T CFET designed with 20 nm metal pitch (MP) offers 62% smaller area and 28% extra speed at iso-power over reference NS devices.

Using an advanced Design Technology Co-Optimization (DTCO) framework, we benchmark gate-all-around Nanosheet (GAA-NS) and Forksheet (FS) architectures at multiple metal pitches (Mx), active widths ($\mathrm{W}_{\mathrm{Ns}}$), and contacting schemes, viz. buried power rail (BPR) and backside power rail (BS-PR) with backside contact (BSC). Interestingly, we find that while at larger cell height (CH), FS perform better than NS, at smaller CH it is the reverse. From a performance perspective, while BSC does not provide any benefit for a wrapped-around contact baseline, it does provide an active width advantage (2 nm extra $\mathrm{W}_{\mathrm{NS}}$). We also introduce a novel GAA-FS device for enhanced gate control and investigate asymmetric-FS for optimized performance at different Mx.

We present TCAD-based methodologies that go beyond process and device simulations of single transistors. We show that TCAD solvers can be used as effective tools to resolve the intricacies of current and future technology nodes that are otherwise difficult to access using EDA-level methods alone.

Design-Technology Co-Optimization (DTCO) emerged as pivotal driver in shaping the state-of-the-art nodes and will gain evermore importance for future technologies. This becomes most evident with the advent of complementary FETs (CFET), a technology which thrives on intricately engineered design and technology to achieve substantial boosts for both logic and memory applications. Practical DTCO implementations are realized by combination of TCAD and SPICE to achieve studies with quick turnaround times (TAT) and for seamless integration with the standard EDA design flow. Here, such a TCAD-to-SPICE DTCO flow is outlined and its application for reliability and variability-aware SRAM and RO is demonstrated.

We present a hierarchical flow for predictive TCAD device simulation in DCTO applications. Using a thoroughly cal-ibrated sub-band Boltzmann transport equation (SBTE) solver, TCAD device simulation parameters for the technology under investigation are generated automatically. This flow enables predictive accuracy of the SBTE solver at turn-around-times of SPICE simulations. It is demonstrated here for an A14 nanosheet technology, i) showing all intermediate calibration details and ii) highlighting a considerable improvement in the accuracy of ring-oscillator performance.

Advancements in the semiconductor industry introduce novel channel materials, device structures, and integration methods, leading to intricate physics challenges when characterizing devices at circuit level. Nevertheless, accurate models for emerging devices are crucial for physics-driven TCAD-to-SPICE flows to enable the increasingly vital design technology co-optimization (DTCO). Particularly for ultra-scaled devices where quantum effects become significant, this led to the introduction of empirical model parameters and a disconnection to manufacturing processes. To catch up with these developments, an alternative to the traditional white-box modeling methods has attracted much attention: machine learning-assisted compact modeling (MLCM). These black-box methods target towards general-purpose modeling of complex mathematics and physics through training of neural networks on experimental and simulated data, generating an accurate closed-form mapping between output characteristics and input parameters for fabrication process and device operation. To address this new trend, this work provides a comprehensive overview of emerging device model methodologies, spanning from device physics to machine learning engines. By analyzing, structuring, and extending distributed efforts on this topic, it is shown how MLCM can overcome limitations of traditional compact modeling and contribute to effective DTCO to further advance semiconductor technologies.

Memories based on a VNAND structure - whether ferroelectric or charge-trap-based - often suffer from performance issues related to the generally poor quality of their polycrystalline silicon (poly Si) channels. In-Ga-Zn-O (IGZO) has been suggested as an alternative material due to its proven history in thin-film applications. In this work TCAD models are developed that model the variability of polycrystalline silicon, amorphous IGZO and polycrystalline ferroelectric HfZrO2 (HZO) thin layers. All models are validated against experimental results and a complete parameter set for the variability models is given. The models are then used to assess the impact of selecting an IGZO-based device over a poly-Si device on the performance of a ferroelectric bit cell.

Using an advanced design technology co-optimization (DTCO) framework, we investigate multi-threshold (multi-$V_{\mathrm{T}})$ options in gate-all-around nanosheet (GAA-NS) FETs at ultra-scaled vertical pitch. This is achieved by allowing inner-gate work-function to be pinned due to very thin metal layers, while only modulating outer-gate work-function. It is shown, that while inner-outer work-function mismatch does result in on-current degradation, the impact is not significant within the mismatch range required (±300 meV) to achieve $3-V_{\mathrm{T}}$ device options. Thus, we propose a path for vertical pitch scaling whereby, higher stacked NS can be processed with relative ease in addition to enhanced performance.

Process technology computer aided design (TCAD) has become an indispensable tool to characterize proposed future technologies. However, current solutions often require tedious manual calibrations of process flows. Here, we present the automatic processing of electron microscopy (EM) images to 2D and 3D device representations. Parts of the device which are not present in the EM image are emulated to create a structure ready for device simulation. The feasibility of this approach is shown by extracting the fin shape from the EM image of a 7nm FinFET, as well as studying the impact of fin shape on device characteristics in an exemplary variability study. Additionally, the inner spacers and gate shape of a nanosheet (NS) FET are reproduced, showcasing the applicability of the presented approach to different device technologies.

Using a full device-technology-co-optimization (DTCO) methodology, we show the advantages of design decoupling of inner $\left(\mathrm{L}_{\mathrm{G}(\mathrm{I})}\right)$- and outer $\left(\mathrm{L}_{\mathrm{G}(\mathrm{O})}\right)$- gates in gate-all-around nanosheet FETs. A better trade-off between short-channel effects ($\mathrm{S}_{S A T}$), external resistance $\left(\mathrm{R}_{\mathrm{EXT}}\right)$, effective favors for a more aggressive $\mathrm{L}_{G(O)}$ scaling (reduces C CARA and/or relaxes contact length, $\mathrm{L}_{\mathrm{CNT}}$) keeping $\mathrm{L}_{\mathrm{G}(\mathrm{I})}$ relaxed (controls $\mathrm{R}_{\mathrm{EFF}}, \mathrm{S}_{\mathrm{SAT}}$). Up to 10% speed-at-iso-leakage, 11% speed-at-iso-power, and 15% power-at-iso-speed gains are possible with this design, in addition to allowing better contact-poly pitch (CPP) scaling path.

We investigated oxide and interface defects of lateral 4H-SiC MOSFETs through capacitance-voltage (C-V) and conductance-voltage (G-V) characterization at various frequencies and temperatures. By employing consecutive up and down sweeps of the gate voltage at three different temperatures, we experimentally characterized the hysteresis width as the difference between up and down sweeps in the depletion to accumulation (d-a) and depletion to inversion (d-i) regions. We observed an increase in the hysteresis width with decreasing temperature. Although the hysteresis width is not affected by the small-signal frequency, at the same time, increasing the frequency leads to a strong stretch-out effect, especially in the d-i region.Our measurement results indicate that the hysteresis deformation of the C-V curves is dominated by three different trap types. First, interface acceptor-like defects located close to the conduction band can follow the small-signal frequency. Slower acceptor-like border traps with trap levels both close to the conduction band and in the middle of the band gap are however responsible for the increase of trapped negative charge with increasing gate voltage. Finally, we assume the presence of a fixed positive charge.

A novel DTCO flow is described with the principal aim to study the impact of air spacer fabrication on the power and performance of a 5-stage inverter ring oscillator at the 7 nm node. The flow incorporates physical and analytical process models from the in-house ViennaPS simulation tool together with device and circuit simulations from GTS Framework's Cell Designer. The air spacer is usually filled by sequential conformal and non-conformal deposition steps. The impact of the thickness of the conformal layer and the sticking probability during non-conformal deposition on the ring oscillator performance is studied here. The air gap, which forms the core of the air spacer, is generated during the non-conformal deposition step. We extract the relative effective permittivity of the air spacer as a function of these two fabrication parameters by solving the Poisson equation to obtain the spacer capacitance. Finally, SPICE model cards are extracted automatically from the TCAD transistor characteristics and the parasitic network is calculated from the full 3D ring oscillator logic cell using a field solver. We apply our framework on two fabrication flows, when the air gap is created before and after the deposition of the first metal contacts layer. We observe that introducing the air gap inside the spacer results in an at-least 15% improvement in the ring oscillator's performance, when the power is kept constant. Further improvements can be achieved by reducing the conformal layer thickness and increasing the sticking probability by increasing the chamber partial pressure or increasing the process temperature.

Charge trapping plays an important role for the reliability of electronic devices and manifests itself in various phenomena like bias temperature instability (BTI), random telegraph noise (RTN), hysteresis or trap-assisted tunneling (TAT). In this work we present Comphy v3.0, an open source physical framework for modeling these effects in a unified fashion using nonradiative multiphonon theory on a one-dimensional device geometry. Here we give an overview about the underlying theory, discuss newly introduced features compared to the original Comphy framework and also review recent advances in reliability physics enabled by these new features. The usefulness of Comphy v3.0 for the reliability community is highlighted by several practical examples including automatic extraction of defect distributions, modeling of TAT in high-k capacitors and BTI/RTN modeling at cryogenic temperatures.