While cryogenic-temperature subthreshold swing (SS) in crystalline semiconductors has been widely studied, a careful study on the temperature-dependent SS in amorphous oxide semiconductors remains lacking. In this paper, a comprehensive analysis of the SS in thin-film transistors with an amorphous indium-gallium-zinc-oxide (IGZO) channel at temperatures from 300 K down to 4 K is presented. Main observations include the following: (1) at room temperature (300 K), the devices exhibit a SS of 61 mV/dec and a low interface trap density of <1011 cm−2. (2) A SS saturation around 40 mV/dec is observed between 200 and 100 K. It is well explained by the electron transport via band tail states with exponential decay (Wt) of 17 meV. (3) At deep cryogenic temperatures, the SS increases significantly, exceeding 200 mV/dec at 4 K. Such high SS values are actually limited by the measurement current range, confirmed by Id − Vg simulations based on the variable range hopping model. This work not only elucidates the SS behavior in amorphous IGZO devices but also provides a deep understanding of the physical mechanisms of electron transport in amorphous semiconductors.

We perform trap density (Dt) extraction through admittance measurements on amorphous Indium-Gallium-Zinc-Oxide (a-IGZO) thin films using multi-finger MOS structures. We investigate the impact of channel length (Lch) on C-V and G-V characteristics and demonstrate a reliable trap density extraction method in short channel devices. The method is validated for pure and Magnesium-doped a-IGZO (Mg:IGZO). The experimental results are consistent with simulations based on a distributed network model.

Ruthenium (Ru) is a noble metal and is known to be resistant to many common chemicals and mixtures. We report in this study a controlled etching/recessing of Ru via wet processing and a combination of dry and wet process using metal-free chemical mixtures. The wet etching study was performed using both as-deposited and annealed atomic layer deposited ruthenium (Ru) films. The etching rate of Ru film in periodic acid mixtures was found to decrease substantially after being annealed at elevated temperatures (300 and 420 degrees C). X-ray photo-electron spectroscopy results indicated that this behavior could be explained by the formation of a thin surface ruthenium oxide layer induced by the thermal anneal. A short treatment in H-2-based atmosphere at elevated temperature or in H-2 plasma rendered the annealed Ru film etchable, explained by the reduction of RuOx film at the surface. The increase in surface roughness after wet etching was most likely caused by the gradual formation of oxidized Ru at the surface. Similarly, non-uniform etching of Ru was also observed for damascene Ru structure with the critical dimension ranging from similar to 12 to 35 nm. An alternative approach using O-2-based plasma achieved a good control of the etching (recessing) depth but also generated a thin layer of "residues" close to the interface between Ru and the liner (TiN). The results from this study have demonstrated that a short H-2 plasma treatment prior to the wet process using the same chemical mixtures was able to etch the modified Ru surface layer together with the interfacial residues selectively to bulk Ru.

The integration of high aspect-ratio (AR) vias or supervias (SV) with a min CD bottom = 10.5 nm and a max AR = 5.8 is demonstrated, allowing a comparison between ruthenium (Ru) and cobalt (Co) chemical vapor deposition (CVD) metallizations. Ru gave a resistance ~2x higher than Co when a 1.1 nm titanium nitride (TiN) film, realized by atomic layer deposition (ALD), was used as an adhesion/nucleation layer. The lowest SV resistance of 56 Ω at the median was obtained with 0.3 nm of titanium oxide (TiOx) ALD and Ru CVD. This configuration gave a 3.4x lower resistance than the equivalent scheme with 0.3 nm TiN ALD and 15% lower resistance than the stacked-via configuration (with 0.3 nm TiOx and Ru fill), meaning that an IR-drop penalty is avoided when compared to the stacked-via approach. A congestion reduction can also be expected from the CD reduction of the SVs as the exclusion area in the intermediate layer can be smaller. Thermal shock tests for both Ru and Co SVs produced no failure after 1000 cycles between −50 °C and 125 °C, and 250 hours.

We evaluate the dielectric reliability performance of 21 nm pitch interconnects integrated in a dense low-k and using a barrierless Ru fill scheme. We show our line-to-line and tip-to-tip TDDB pass 10 years of lifetime at 0.75 V for technology relevant line lengths and number of tips, respectively. Intrinsic dielectric breakdown without metal drift is demonstrated using BTS-TVS measurements. We also investigate the impact of dielectric scaling towards lower dimensions using planar capacitor structures. We observe an increasing field acceleration factor with decreasing thickness possibly suggesting different, slower, degradation mechanisms being present in the thinner dielectrics leading towards more reliability margin for scaled interconnects.

Hafnium aluminates films with 50 mol% of Hf were deposited onto Si(100) using atomic layer deposition. The films were annealed by RTP at 1000 oC for 60 s in pure N2 or N2+5%O2 and by LASER at 1200oC for 1ms in pure N2. Then, they were characterized by X-ray spectroscopies, ellipsometry, Rutherford backscattering and scanning electron microscopy. For thin films annealed by RTP in N2, phase separation takes place, promoting the formation of HfO2 and Al2.4 O3.6 crystalline phases. In contrast, the films annealed by LASER remain predominantly amorphous with crystalline facets of Al2.4O3.6. Also, non-homogeneous distribution of the chemical elements within the dielectrics gave rise to the formation of several regions which can be viewed as sub-layers, each of them with arbitrary electron density and thickness. As a result, Kratky curves pointed out to the coexistence of different features described by different gyration radius yielding GISAXS scattering profiles with polydispersive characteristics. Finally, the samples annealed by RTP were interpreted as agglomerates of spheroids with different sizes (1.1-2.2 nm) and with different crystalline phases whereas the samples annealed by LASER were interpreted as larger spheroids of crystalline Al2.4O3.6 (1.7-2.7nm) embedded in a matrix predominantly amorphous.

The integration of high-aspect-ratio (AR) supervias (SV) into a 3 nm node test vehicle, bypassing an intermediate 21 nm pitch layer, is demonstrated. Place-and-route (PnR) simulations of the Power Delivery Network (PDN) proved IR-drop reduction with respect to the stacked-via configuration. SV first and SV last integration approaches were electrically tested using full barrierless ruthenium (Ru) on a dielectric low-k 3.0. A maximum AR = 3.8 was achieved with ~2.4 times lower resistance than the alternative stacked-via configuration. Thermal shock tests produced no SV failure after 1000 cycles between -50 °C and 125 °C, and 250 hours. Time-dependent-dielectric-breakdown (TDDB) tests between SV and M2 lines gave a TTF 63.2% (at 1 MV/cm) > 10 years, when 3 M2 tracks are blocked.

In this work we present a comparative study of two processes for the fabrication of an array of microchannels for microfluidics applications, based on integrated-circuit technology process steps, such as lithography and dry etching. Two different methods were investigated in order to study the resulting microstructures: wet and dry deep etching of silicon substrate. The typical etching depth necessary to the target application is 50 μm.

Nowadays, the direct bonding process is embedded in a BEOL manufacturing process where the maximum temperature is 400°C. For certain applications there is the need to lower such thermal budget. One of the first process steps which will be modified will be the bonding layer deposition step as well as the densification step. It is known that by lowering the deposition temperature the quality of the dielectric will be decreased as well. This change will have a direct consequence on the bonding process which relies on the quality of the dielectric. It is found that if we use a post bond anneal temperature which exceeds the densification temperature voids originate at the bonding interface. By means of FTIR studies and ERD analysis the origin of the voids is tentatively ascribed to H or H related species. These findings provide a basic understanding on how to tune the deposition condition to select a proper low temperature dielectric which will enable us to obtain a good bonding uniformity and a good bond strength for the described application.

Surface activated bonding is more and more attractive as a key technology to realize higher performance CMOS devices independent of scaling. The major challenge of dielectric bonding is to decrease the process temperature in order to be compatible with CMOS processing. In the past, we demonstrated low temperature bonding using SiCN as interfacial dielectric layer, where we have obtained a bond energy above 2.2 J/m(2) with a post bond annealing process of 250 degrees C. In this work, the composition of SiCN was varied aiming at the identification of the key elements taking part in the bonding mechanism. The film density, roughness, CMP outcome, water contact angle and impact of plasma activation have been investigated on three different compositions of SiCN. Bond energy above 2.5 J/m(2) is obtained for the carbon rich SiCN film. (c) The Author(s) 2019. Published by ECS. This is an open access article distributed under the terms of the Creative Commons Attribution 4.0 License (CC BY, http://creativecommons.org/licenses/by/4.0/), which permits unrestricted reuse of the work in any medium, provided the original work is properly cited.

The integration of a three-layer BEOL process which includes an intermediate 21 nm pitch level, relevant for the 3 nm technology node, is demonstrated. A full barrier-less Ruthenium (Ru) dual-damascene (DD) metallization allowed to test different dimensions of minimum island, via extension and tip-to-tip (T2T). Five-track place and route (PNR) and SRAM constructions were realized with the self-aligned block (SAB) technique. Stacked vias showed resistance modulation with the size of the minimum island due to the change in via chamfer. High aspect ratio supervias (SV), to bypass M2 and directly link M1 to M3, were tested with different metallization schemes. Line-to-line and T2T reliability tests passed the 10- year lifetime predictions. Finally, electromigration (EM) tests on SV showed no failures after 140 hours of accelerated stress conditions.

The semiconductor scaling roadmap shows the continuous node to node scaling to push Moore's law down to the next generations. In that context, the foundry N5 node requires 32nm metal pitch interconnects for the advanced logic Back-End of Line (BEoL). 193immersion usage now requires self-aligned and/or multiple patterning technique combinations to enable such critical dimension. On the other hand, EUV insertion investigation shows that 32nm metal pitch is still a challenge but, related to process flow complexity, presents some clear motivations. Imec has already evaluated on test chip vehicles with different patterning approaches: 193i SAQP (Self-Aligned Quadruple Patterning), LE3 (triple patterning Litho Etch), tone inversion, EUV SE (Single Exposure) with SMO (Source-mask optimization). Following the run path in the technology development for EUV insertion, imec N7 platform (iN7, corresponding node to the foundry N5) is developed for those BEoL layers. In this paper, following technical motivation and development learning, a comparison between the iArF SAQP/EUV block hybrid integration scheme and a single patterning EUV flow is proposed. These two integration patterning options will be finally compared from current morphological and electrical criteria.

Porous oxide films were deposited by reactive sputtering. Some films received UV cures and/or a Si cap. The FTIR analyses show that the deposited films were very hydrophilic. Standard ellipsometric porosimetry was not able to determine porosity nor pore size. With GISAXS, the porosity of different films was determined (approximately 13%) and the pore format (mostly spherical pores with a radius of approximately 5 nm). Electrochemical Impedance Spectroscopy completed the pore analysis, indicating mostly open porosity. These techniques were sufficiently sensitive to show that the Si cap closed the pores somewhat while the UV cure increased the porosity.

The structure, crystallinity, and properties of as-deposited two-dimensional (2D) transition metal dichalcogenides are determined by nucleation mechanisms in the deposition process. 2D materials grown by atomic layer deposition (ALD) in the absence of a template are polycrystalline or amorphous. Little is known about their nucleation mechanisms. Therefore, the nucleation behavior of WS2 during plasma enhanced ALD from WF6, H2 plasma, and H2S at 300 °C is investigated on amorphous ALD Al2O3 starting surface and on monocrystalline, bulk sapphire. Preferential interaction of the precursors with the Al2O3 starting surface promotes fast closure of the WS2 layer. The WS2 layers are fully continuous at WS2 content corresponding to only 1.2 WS2 monolayers. On amorphous Al2O3, (0002) textured and polycrystalline WS2 layers form with grain size of 5 to 20 nm due to high nucleation density (∼1014 nuclei/cm2). The WS2 growth mode changes from 2D (layer-by-layer) growth on the initial Al2O3 surface to three-dimensional (Volmer–Weber) growth after WS2 layer closure. Further growth proceeds from both WS2 basal planes in register with the underlying WS2 grain, and from or over grain boundaries of the underlying WS2 layer with different in-plane orientation. In contrast, on monocrystalline sapphire, WS2 crystal grains can locally align along a preferred in-plane orientation. Epitaxial seeding occurs locally albeit a large portion of crystals remain randomly oriented, presumably due to the low deposition temperature. The WS2 sheet resistance is 168 MΩ μm, suggesting that charge transport in the WS2 layers is limited by grain boundaries.

When two-dimensional (2D) group-VI transition metal dichalcogenides such as tungsten disulfide (WS2) are grown by atomic layer deposition (ALD) for atomic growth control at low deposition temperatures (<= 450 degrees C), they often suffer from a nanocrystalline grain structure limiting the carrier mobility. The crystallinity and monolayer thickness control during ALD of 2D materials is determined by the nucleation mechanism, which is currently not well understood. Here, we propose a qualitative model for the WS2 nucleation behavior on dielectric surfaces during plasma-enhanced (PE-) ALD using tungsten hexafluoride (WF6), dihydrogen (H-2) plasma and dihydrogen sulfide (H2S) based on analyses of the morphology of the WS2 crystals. The WS2 crystal grain size increases from similar to 20 to 200 nm by lowering the nucleation density. This is achieved by lowering the precursor adsorption rate on the starting surface using an inherently less reactive starting surface, by decreasing the H-2 plasma reactivity, and by enhancing the mobility of the adsorbed species at higher deposition temperature. Since silicon dioxide (SiO2) is less reactive than aluminum oxide (Al2O3), and diffusion and crystal ripening is enhanced at higher deposition temperature, WS2 nucleates in an anisotropic island-like growth mode with preferential lateral growth from the WS2 crystal edges. This work emphasizes that increasing the crystal grain size while controlling the basal plane orientation is possible during ALD at low deposition temperatures, based on insight in the nucleation behavior, which is key to advance the field of ALD of 2D materials. Moreover, this work demonstrates the conformal deposition on three-dimensional (3D) structures, with WS2 retaining the basal plane orientation along topographic structures.

In this study, the mechanical integrity of advanced multilayer nano-interconnects, as metal/dielectric nano composites, was investigated using a combination of analytical modelling, computational mechanics and ex periments. A method for fast derivation of the effective orthotropic elastic moduli of complex multilayer nano interconnects was demonstrated and corroborated using finite element modelling (FEM). Subsequently, the of fective elastic properties were employed for homogenization and course-graining in computational fracture mechanics models. This allowed the model development and simulation time to be reduced drastically and also enabled the global delamination behavior in nano-interconnects to be predicted consistent with experimental results. The study identified the via layers integrated with ultra low-k (ULK) dielectrics as the delamination prone layers. Particularly, failure analysis following exposure to bump shear tests revealed that the via layer adjacent to the top stiff layers was the dominant fracture path. By using analytical and computational mechanics it is shown that the elasticity mismatch between the soft intermediate group of layers and the stiff top group of layers dictates this delamination mode. Detailed FE modeling, showed that when vias are uniformly distributed, increasing the via density by only a few percent will increase the mechanical integrity drastically. Delamination experiments revealed a statistically significant increase of critical fracture energy (G(c)) of ULK dielectric films when their thickness is reduced. Thus, reducing the thickness of the via layers, will also increase their effective G(c). However, analytical modelling together with experiments indicate that this trend will apply down to an optimal via layer thickness of approximately 30 nm where the G(c) is predicted to reach its theoretical maximum in the case of organosilicate glass ULK (OSG 2.55).

Surface activated dielectric bonding is more and more attractive as a key technology to achieve further high-performance CMOS based devices independent on scaling. The major challenge of dielectric bonding is to decrease the process temperature in order to be compatible with CMOS processing. Although the conventional SiO2-SiO2 bonding has already been comprehensively investigated, there might be some limitations in terms of thermal budget. In the past, we have demonstrated low temperature bonding using PECVD-SiCN as interfacial layer, where we have obtained more than 2200 mJ/m2 of adhesion energy at 250 oC of post annealing temperature [1]. In this work, the composition of SiCN has been tuned aiming at the identification of the key elements taking part in the bonding mechanism and to further increase the adhesion energy. The SiCN composition was successfully controlled by tuning the CVD deposition process, as it is proven by elastic recoil detection (ERD) measurements which enable us to monitor the ratio of the different elements (C,N,H,O, Si) in the different films. A table with ERD results is reported below. Also, the film densities are determined by using the mass differences of the processed wafers. The density becomes lower with increasing carbon concentration. The density variation impacts the CMP removal rate, which is critical for actual hybrid bonding process. On the other hand, no difference on the roughness is seen for all SiCN films. After film planarization by CMP, wafer bonding test were done on 300 mm wafers by combining a pair of the same films as interfacial layer. Prior to bonding, N2 plasmas were applied on the both surfaces. No voids were observed for all the pairs, even after post bond annealing. The highest bonding strength is obtained from the carbon rich SiCN (SiCN #2). This indicates that the higher adhesion by SiCN may be attributed to the carbon dangling bond formed by plasma activation, rather than hydrogen or nitrogen. Further mechanisms are discussed to understand the present low-temperature bonding technique. [1] E. Beyne et.al., “Scalable, sub 2µm Pitch, Cu/SiCN to Cu/SiCN Hybrid Wafer-to-Wafer Bonding Technology” IEEE IEDM 2017, 32.4.1 (2017) Figure 1

We demonstrate an integration approach to enable 16nm half-pitch interconnects suitable for the 5nm technology node using 193i Lithography, SADP, SAQP, three times Litho-Etch (LE3) and tone-inversion. A silicon-verified DOE experiment on a SAQP process suggests a tight process window for core etch and spacer depositions. We also show a novel process flow which enable us to pattern tight-pitch metal-cut (block), and effectively scale the trench CD to 12nm at pitch 32nm. Finally we discuss line resistance and resistivity obtained for the 16nm and 12nm trenches created using 193i integration flow.

Polymer grafting of pore sidewalls is studied as a protecting agent against processing damage. Polymethyl-methacrylate (PMMA), an improved polystyrene (PS-pro), and a tailored plasma damage management polymer (PDM) are considered as potential candidates. PMMA and PS-pro show nonhomogeneous grafting properties, while PDM coat the pore sidewalls uniformly through the bulk of the porous low-k film. A k ∼ 2.2 porous spin-on glass is used as a vehicle for processing damage study. Approximately one monolayer is grafted on the pore walls, leading to a k-value increase up to Δk ∼ 0.2. Using grafted PDM, the porous low-k chemical stability in 0.5% diluted hydrofluoric acid is significantly improved. Concerning plasma damage, at constant etch depth methyl depletion is decreased, mainly in capacitive coupled plasma discharge showing high polymerizing character, leading to similar damage depth as found for a reference organo-silicate glass 2.7 low-k. However, moisture uptake is not improved, leading to significant drift in the dielectric constant.