The design methodology called design for manufacturing (DFM) includes a set of techniques to modify the design of integrated circuits (ICs) in order to make them more manufacturable, i.e., to improve their functional yield, parametric yield, or their reliability. Traditionally, in the pre-nanometer era, DFM consisted of a set of different methodologies trying to enforce some soft design rules regarding the shapes and polygons of the physical layout of an IC product. The chapter focuses on the DFM requirements for technologies in the nanometer range where the spectrum of physical phenomena that may impact manufacturability of products is mind-boggling. It shows that the systematic characterization of these phenomena and their impact on IC yield and performance is of crucial importance for true DFM. Model-based, proactive DFM philosophy consists in the development of accurate, silicon-verified Yield loss mechanism (YLM) models that can evaluate the relative impact of each YLM and assess trade-offs.

Detection and monitoring of the yield loss mechanisms and defects in product chips have been a subject of extensive efforts, resulting in multiple useful Design-for-Manufacturing (DFM) and Design-for-Test (DFT) techniques. Defect inspection techniques extend optical inspection further into sub-10 nm nodes, but many buried defects are formed as a result of multi-layer 3-D interaction, and they are difficult to detect by surface optical scans. In case of a functional failure related to a defect (an open or a short), the localization of the fail site for failure analysis and root cause identification is often difficult, especially for random logic design. In this paper we describe a new -DFM methodology which inserts into the product design special test structures to support New Product Introduction (NPI) and a product yield ramp. The structures are part of PDF Solutions’ proprietary Design-for-Inspection (DFI) system with no penalty to the product layout. They are designed to be electrically tested in a non-contact way using a dedicated and specially optimized e-Beam tool. The layouts of these structures are based on the standard cell design therefore they can be used as filler cells in standard cell-based logic designs. The paper presents the concept of the test structures and their design to cover specific failure modes and enable fail mechanism identification. We describe the design flow to integrate the structures into the product floorplan and the non-contact test methodology to scan product wafers and detect failures. Finally, we demonstrate usage of such DFI structures and provide results collected from scanning product wafers containing embedded DFI filler cells.

Arguably, SiC technology is the most rapidly expanding IC manufacturing technology driven mostly by the aggressive roadmap for battery electric vehicle penetration and also industrial high-voltage/high-power applications. This paper provides a comprehensive overview of the state of the art of SiC technology focusing on the challenges starting from the difficult and lengthy SiC substrate growth all the way to the complex MOSFET assembly processes. We focus on the differentiation from the established Si manufacturing processes and provide a comprehensive list of references as well as a brief description of our own research into the key manufacturing processes in this technology. We also present a SiC technology and product roadmap.

This study presents a new type of silicon-embedded chip health monitoring sensors. They extend data collection well beyond typically assessed, to include such important factors as mechanical stress, reliability indicators, and gate to contact proximity. The sensors are part of CV Core® system, and their implementation is demonstrated with examples obtained from 7nm and 12nm FinFET products. The results demonstrate unique capabilities to monitor chip health across the whole life cycle.

The paper describes how the semiconductor product yield analysis evolved from simple one-way correlation analysis limited by siloed data into powerful cloud based and AI/ML enhanced analytics tool. We discuss the tasks and efforts needed to align all data types, create the Big Data accessible repositories, and deploy end-to-end analytics, updating the AI/ML models using incoming new yield data stream.

The paper describes a new type of in-die monitor sensors for in-situ detection of changes in the level of mechanical stress experienced by silicon product die. Multiple sensors have been distributed across a 3x3 mm2 die manufactured with 12nm FinFET technology. The changes in mechanical stress were monitored with measurements at wafer-level, and after dicing and thinning, and chip packaging. The results showed that the stress change depends on wafer thinning, and after packaging has a nonuniform distribution across the chip. We propose to use this characterization solution for process optimization for heterogeneous integration and monitoring chip packaging through dicing, bonding, and molding.

This paper presents a novel methodology called Design-for-Inspection (DFI) that enables sensitive inline pickup for failure mechanisms previously undetectable until product test (wafer sort, final test, HTOL) or field failures. Dummy filler cells are replaced in the physical design flow by DFI-enabled filler cells which are designed to be sensitive to specific failure modes without any area penalty. To achieve very high inspection throughput, we have developed a proprietary vector scanning eBeam Voltage Contrast tool called eProbe 250 which is capable of inspecting up to 5 billion Devices Under Test (DUT) per hour. Due to novel processing of gray levels the system is capable of detecting not only the hard defects such as shorts or opens, but also the soft failures, namely leakages and resistive contacts and vias. We illustrate this methodology by several examples from the most recent FinFET technology nodes.

PDF’s electrically testable structures, called Characterization Vehicles™ (CV’s), have been extremely successful in characterizing printability windows of the leading- edge technologies for the last 15 years. We have been able to demonstrate clear correlations between the electrical misalignment data and product yield for several technology generations and these CV’s have been employed in all leading foundries. However, their placement is limited to the scribe lines and in many fabs they are tested only at the end of wafer processing. We have conducted many experiments that demonstrated their accuracy vs. the cross-sectional TEM and concluded that the final edge placement error (EPE) does not always correlate to in-line overlay measurements, and often exceeds by far the allowable tolerances, leading to the product yield loss. With the multiple patterning schemes and recently EUV, there is a clear need to fully characterize the EPE budget in the technology development and, if this information is available in-line, use this information for process control by feeding it back to the scanners. Over the last 8 years a new technology called Design For Inspection™ (DFI) has been developed and already proven in all major foundries. Specially designed test structures are placed within the product die in place of the filler cells and dummy fill without any area penalty, as well as in the scribe lines, which allows for the EPE monitoring with sub-Design Rule designs. All DFI structures are tested with a custom (designed and manufactured by PDF) eBeam voltage contrast tool with a very high speed and sub-nm resolution for the EPE characterization. The new vector scan eProbe-250 tool is capable of testing billions of DFI structures sites with a speed up to 5 billion sites/hour on a single wafer. Contrary to the typical eBeam machines, it utilizes the gray scale data from the tool to allow for the marginality extraction (soft failures which may have significant reliability impact). This allows for extensive Design of Experiment (DoE) to be performed to fully characterize the EPE and other process marginalities. This DFI methodology has been enthusiastically received by not only foundries but also leading fabless companies and more than 20 tape-outs of MultiProduct Wafers (MPW’s) and actual product wafer scribes have been already executed proving the value of this methodology from the 14nm down to 5 nm nodes. This methodology has been currently applied to the EUV characterization where the overlay and local LER variations contribute the most to the EPE budget.

We have developed a new reliability monitoring suite, within a proprietary IP block that we call a CV® Core, with aging sensors embedded in the product layout and testable through the product I / O interface. We illustrate the application of the sensor suite with an example of the PMOS NBTI monitor, testable at the wafer level during product electrical wafer sort (EWS), as well after packaging at final test or during burn-in. During EWS, the wafer-level stress test can be used to identify a marginal chip, help material dispositioning for burn-in, or support additional grading for chiplet matching for multi-chip modules. The aging sensors can also be used during the chip lifetime to monitor the device wear-out and alarm users about abnormal silicon aging rates against target mission profile. In this work, we show the wafer level test results for PMOS transistor degradation rates under NBTI stress, within wafer variability, and correlation of degradation rates between sensors stressed under different conditions.

In this paper, we report an advanced e-beam defect inspection tool (eProbe®250) and the Design-for- Inspection™ (DFI) system that has been built and deployed by PDF Solutions down to 4nm FinFET technology nodes. This tool has a very high throughput which allows for in-line inspection of nanometer level defects in the most advanced technology nodes. We also present eProbe applications for detection of systematic buried defects and process window characterization.

Advanced IC’s built with recent technology nodes take advantage of the process induced mechanical stress, which is used as one of the transistor performance boosters. Modulation of the stress level, experienced by silicon chip, has significant impact on its performance and reliability. Therefore, monitoring of this stress through wafer manufacturing and packaging process is of high importance. We have developed an in-die-embedded stress sensor, testable with standard product test that can with help measuring and monitoring stress level in the die. The sensor design was demonstrated for multiple advanced FinFET technology nodes (< 14nm). We have confirmed high sensitivity across process corners and temperature with consistent results between electrical wafer sort (EWS) and final test (FT). The results from the mechanical stress sensors indicate that the stress non-uniformity across the wafer is preserved through wafer dicing/thinning/packaging process. Statistical analysis of the sensor results enables detection of wafer patterns and outlier identification at EWS and subsequent FT after assembly enables detection of abnormal mechanical stress changes due to packaging. This mechanical stress sensor provides differentiated data for EWS, FT, and Burn-In (BI) to create product relevant screening specs for improved product reliability and can provide an early alarm for the product reliability risk due to effects such as delamination or cracks. This sensor has been implemented in the PDF Solutions’ CV Core ® system which enables for in-field tracking and analyzing the sensor signals to detect and mitigate the potentially disastrous reliability failures.

Layout Design Rules have been scaled very aggressively to enable the 7nm technology node without EUV. As a result, achieving acceptable performance and yield in High Volume Manufacturing (HVM) has become an extremely challenging task. Systematic yield and parametric variabilities have become quite significant. Moreover, due to overlay tolerance requirements and diminishing process windows, reliability risks due to soft shorts/leakages and soft opens for both FEOL and BEOL have also increased to a critical level. Introduction of EUV at the second wave of 7nm and 5nm will not help significantly due to increased detectivity and significant increases in Local Edge Roughness. New characterization techniques are necessary to identify the yield and reliability risks. After reviewing the evolution of design rules and classifying the yield and reliability risks, we will present examples from Design-For-Inspection™ (DFI™) and the novel VarScan methodology to "detect the undetectable" defects and characterize variability for both FEOL and BEOL 7nm and below technologies.

When we analyze the scaling factors of the recent technology nodes, we come to the conclusion that the geometrical scaling scenario has been replaced by the electrical scaling and hence the electrical characterization of these really challenging technologies becomes an absolute must. However, the extremely small process windows, and the 3-dimensional nature of the FinFET devices and the complicated interconnect schemes, make this characterization very difficult. Systematic failure modes and their dependence on the layout patterns are extremely complex and almost impossible to detect in-line. Moreover, soft failures become much more prevalent due to process marginalities and present not only yield but also reliability hazards. Hence, the new fault models must be created that take into account layout patterns and layout-process interactions to allow for more efficient testing and reliability risk screening. This talk will present novel approaches to electrical characterization of the dominant failure modes, its impact on the test generation and execution, and the need for tracking this information all the way from the front end process to the test and assembly stages of IC manufacturing.

Efficiency and manufacturability of standard cell logic is critical for an IC, as standard cells are at the heart of the nexus between technology definition, circuit design and physical synthesis. Conventional standard cell design techniques are increasingly ineffective as we scale to patterning restricted sub-20 nm CMOS nodes. To meet the constraints and leverage the features of future technology offerings, we propose a holistic design technology co-optimization (DTCO) for standard cell logic. In our holistic DTCO we co-optimize the standard cell architecture to balance manufacturability and efficiency at the cell level while taking into account block level considerations such as pin accessibility and power rail robustness. Our DTCO in a foundry 14 nm CMOS resulted in two standard cell architectures, namely, 10T_BiDir and 10T_UniDir. We evaluated these cell libraries with physically synthesized blocks and ring oscillator test structures in IBM 14SOI process. We observed that 10T_BiDir emerges as the preferred alternative at 14 nm CMOS, with 10T_UniDir promising better scalability to future nodes.

Following Intel's lead in the 22nm technology, it seems that the industry has decided that the junction-isolated FinFET on bulk is the dominant technology for the next two nodes, namely 14 and 10nm. In this talk, we will examine the reasoning behind such decision and evaluate the likelihood of alternative solutions such as dielectrically-isolated FinFET and FDSOI/UTBB for a broad spectrum of high volume products driving the semiconductor industry.

Given the deployment delays for EUV, several next generation lithography (NGL) options are being actively researched. Several cost-effective NGL solutions, such as self-aligned double patterning through sidewall image transfer (SIT) and directed self-assembly (DSA), in conjunction with process integration challenges, mandate grating-like pattern design. As part of the GRATEdd project, we have evaluated the design cost of grating-based design for ASICs (application specific ICs). Based on our observations we have engineered fundamental changes to the primary ASIC design components to make scaling affordable and useful in deeply scaled sub-20 nm technologies: unidirectional-M1 based standard cells, application-specific smart SRAM synthesis, and statistical and self-healing analog design.

In this paper, we propose a methodology based on unsupervised learning for automatic clustering of wafer spatial signatures to aid yield improvement. Our proposed methodology is based on three steps. First, we apply sparse regression to automatically capture wafer spatial signatures by a small number of features. Next, we apply an unsupervised hierarchical clustering algorithm to divide wafers into a few clusters where all wafers within the same cluster are similar. Finally, we develop a modified L-method to determine the appropriate number of clusters from the hierarchical clustering result. The accuracy of the proposed methodology is demonstrated by several industrial data sets of silicon measurements.