An efficient Pathfinding DTCO analysis flow which allows rapid block-level power, performance, and area (PPA) characterization is presented. To optimize this flow for the exploration of innovative technology-architecture definitions, i.e. new devices and their integration into functional logic cells, the time consuming task of generating and validating a process design kit (PDK) for each technology definition is eliminated by taking advantage of automated standard cell generation and direct emulation-based parasitic extraction. Further efficiency gains are obtained through a customized flow that allows a large number of place and route ( PnR) experiments to be executed automatically. The efficiency of the presented Pathfinding DTCO flow is demonstrated in experiments quantifying block-level PPA changes in different implementations of finFET and CFET devices.

New tools and methodologies are fused with conventional elements of the process-design-kit (PDK) and design enablement to introduce a rigorous yet fast and agile technology prototyping platform. This design technology co-optimization (DTCO) solution replaces the rigid, time and resources consuming PDK to enhance the core functions critical to evaluate power, performance area and cost (PPAC). Any technology definition with any device or process integration innovation can be evaluated at the standard cell level first, and then at the block level to explore and understand the requirements of different design applications. The flexibility and fast turn-around make it practical to imagine, test and compare many technology prototypes. From simple evolutions to innovative disruptions, the feasibility and value of the technology choices and hardware tools required can be identified early with great detail, significantly accelerating the development of future process tools. To illustrate the efficiency of the platform, complementary-FET (CFET) [1] technologies are compared to reference finFET technologies. As we approach the fundamental limits of dimensional scaling, with so many choices ahead of us including 3D constructs, we need efficient technology prototyping to navigate and steer in the right direction.

This paper describes a rigorous yet flexible standard cell place-and-route flow that is used to quantify block-level power, performance, and area trade-offs driven by two unique cell architectures and their associated design rule differences. The two architectures examined in this paper differ primarily in their use of different power-distribution-networks to achieve the desired circuit performance for high-performance logic designs. The paper shows the importance of incorporating block-level routability experiments in the early phases of design-technology co-optimization by reviewing a series of routing trials that explore different aspects of the technology definition. Since the electrical and physical parameters leading to critical process assumptions and design rules are unique to specific integration schemes and design objectives, it is understood that the goal of this work is not to promote one cell-architecture over another, but rather to convey the importance of exploring critical trade-offs long before the process details of the technology node are finalized to a point where a process design kit can be published.

Although lens aberrations in EUV imaging systems are very small, aberration impacts on pattern placement error and overlay error need to be carefully investigated to obtain the most robust lithography process for high volume manufacturing. Instead of focusing entirely on pattern placement errors in the context of a single lithographic process, we holistically study the interaction between two sequential lithographic layers affected by evolving aberration wavefronts, calculate aberration induced overlay error, and explore new strategies to improve overlay.

This presentation will review the key aspects of advanced photomask manufacturing and highlight the major technical challenges facing the mask industry. The bulk of the discussion will focus on mask technology for optical (248nm - 193nm wavelength) lithography, seen industry wide as the front up approach for 250nm to 180nm wafer dimension processing. After briefly establishing the business environment in which advanced optical mask development is done, current and future mask specifications are presented, the basic chrome on glass mask process is reviewed, and the major technical challenges facing each process segment are discussed in the context of high resolution lithography requirements. The basic principles involved in the two most mask intensive resolution enhancement techniques, optical proximity correction and phase shifted masks (alternating as well as attenuated) are reviewed and their specific technology challenges presented. A brief discussion of mask challenges in proximity x-ray lithography, the only viable near in alternative to optical lithography for this resolution range, will close out this presentation. The material is targeted at the general VLSI manufacturing and development community, it is not intended as a training course for mask development engineers.

Vertically-stacked horizontal gate-all-around (GAA) Nanosheet structures have been recognized as good candidates for beyond the 7nm technology node to achieve improved power-performance and area scaling compared to FinFET technologies. Full realization of device-performance entitlement in high-performance and high-density chip designs is, therefore, of critical importance. In this paper, we present a quantitative performance evaluation of horizontal Nanosheet structures focused on key design styles as well as unique Nanosheet challenges such as gate-resistance. This analysis was performed with a fully developed design kit over a wide range of sub-7nm design, including various cell heights, as well as design features such as M1 power staples and performance-aware designs for smaller track cells.

The initial readiness of EUV patterning was demonstrated in 2016 with IBM Alliance's 7nm device technology. The focus has now shifted to driving the 'effective' k1 factor and enabling the second generation of EUV patterning. Thus, Design Technology Co-optimization (DTCO) has become a critical part of technology enablement as scaling has become more challenging and the industry pushes the limits of EUV lithography. The working partnership between the design teams and the process development teams typically involves an iterative approach to evaluate the manufacturability of proposed designs, subsequent modifications to those designs and finally a design manual for the technology. While this approach has served the industry well for many generations, the challenges at the Beyond 7nm node require a more efficient approach. In this work, we describe the use of “Design Intent” lithographic layout optimization where we remove the iterative component of DTCO and replace it with an optimization that achieves both a “patterning friendly” design and minimizes the well-known EUV stochastic effects. Solved together, this “design intent” approach can more quickly achieve superior lithographic results while still meeting the original device’s functional specifications. Specifically, in this work we will demonstrate “design intent” optimization for critical BEOL layers using design tolerance bands to guide the source mask co-optimization. The design tolerance bands can be either supplied as part of the original design or derived from some basic rules. Additionally, the EUV stochastic behavior is mitigated by enhancing the image log slope (ILS) for specific key features as part of the overall optimization. We will show the benefit of the “design intent approach” on both bidirectional and unidirectional 28nm min pitch standard logic layouts and compare the more typical iterative SMO approach. Thus demonstrating the benefit of allowing the design to float within the specified range. Lastly, we discuss how the evolution of this approach could lead to layout optimization based entirely on some minimal set of functional requirements and process constraints.

The economic health of the semiconductor industry requires substantial scaling of chip power, performance, and area with every new technology node that is ramped into manufacturing in two year intervals. With no direct physical link to any particular design dimensions, industry wide the technology node names are chosen to reflect the roughly 70% scaling of linear dimensions necessary to enable the doubling of transistor density predicted by Moore’s law and typically progress as 22nm, 14nm, 10nm, 7nm, 5nm, 3nm etc. At the time of this writing, the most advanced technology node in volume manufacturing is the 14nm node with the 7nm node in advanced development and 5nm in early exploration. The technology challenges to reach thus far have not been trivial. This review addresses the past innovation in response to the device challenges and discusses in-depth the integration challenges associated with the sub-22nm non-planar finFET technologies that are either in advanced technology development or in manufacturing. It discusses the integration challenges in patterning for both the front-end-of-line and back-end-of-line elements in the CMOS transistor. In addition, this article also gives a brief review of integrating an alternate channel material into the finFET technology, as well as next generation device architectures such as nanowire and vertical FETs. Lastly, it also discusses challenges dictated by the need to interconnect the ever-increasing density of transistors.

As pitch scaling is becoming constrained not only by lithographic resolution limits but also by fundamental device and interconnect challenges, the semiconductor industry has turned to cell-height reduction as a means of achieving competitive area scaling. The risk in using cell-height reduction to compensate for insufficient pitch scaling is that place and-route inefficiencies caused by wiring congestion at the block level of the design can easily eliminate any area scaling gains made at the cell level of the design. This paper shows how careful cell-architecture optimization, physical design methodology changes, and place-and-route innovations have led to competitive block level area scaling for 7nm technology nodes and beyond. Data is presented to show that an entire node's worth of scaling can be achieved through these comprehensive design-technology co-optimization efforts.

Design technology co-optimization (DTCO) is the term used to describe the process of deriving a competitive technology definition out of a number of increasingly complex trade-offs. DTCO is not a specific approach or methodology, but rather a commitment to closer collaboration between designers and process engineers born out of necessity to maintain value in semiconductor scaling. This paper aims to clarify this abstract concept through a series of examples encountered in scaling a logic cell from the N14 to the N3 technology node.

We present a 7nm technology with the tightest contacted poly pitch (CPP) of 44/48nm and metallization pitch of 36nm ever reported in FinFET technology. To overcome optical lithography limits, Extreme Ultraviolet Lithography (EUV) has been introduced for multiple critical levels for the first time. Dual strained channels have been also implemented to enhance mobility for high performance applications.

Design rules are created considering a wafer fail mechanism with the relevant design levels under various design cases, and the values are set to cover the worst scenario. Because of the simplification and generalization, design rule hinders, rather than helps, dense device scaling. As an example, SRAM designs always need extensive ground rule waivers. Furthermore, dense design also often involves "design arc", a collection of design rules, the sum of which equals critical pitch defined by technology. In design arc, a single rule change can lead to chain reaction of other rule violations. In this talk we present a methodology using Layout Based Monte-Carlo Simulation (LBMCS) with integrated multiple ground rule checks. We apply this methodology on SRAM word line contact, and the result is a layout that has balanced wafer fail risks based on Process Assumptions (PAs). This work was performed at the IBM Microelectronics Div, Semiconductor Research and Development Center, Hopewell Junction, NY 12533

For the past four decades, cost and features have driven complementary metal-oxide semiconductor (CMOS) scaling. Severe lithography and material limitations seen below the 20-nm node, however, are challenging the fundamental premise of affordable CMOS scaling. Just continuing to co-optimize leaf cell circuit and layout designs with process technology does not enable us to exploit the challenges of sub-20-nm CMOS. For affordable scaling, it is imperative to work past sub-20-nm technology impediments while exploiting its features. To this end, we propose to broaden the scope of design technology co-optimization (DTCO) to be more holistic by including microarchitecture design and computer-aided design, along with circuits, layout, and process technology. Furthermore, we undertook such a holistic DTCO for all critical design elements such as embedded memory, standard cell logic, analog components, and physical synthesis in a 14-nm process. Measurements results from experimental designs in a representative 14-nm process from IBM demonstrate the efficacy of the proposed approach. (C) 2015 Society of Photo-Optical Instrumentation Engineers (SPIE)

Due to elongated delay of extreme ultraviolet lithography (EUVL), the semiconductor industry has been pushing the 193nm immersion lithopgrahy using multiple patterning to print critical features in 22nm/14nm technology nodes and beyond. Multiple patterning lithography (MPL) poses many new challenges to both mask design and IC physical design. The mask layout decomposition problem has been extensively studied, first on double patterning, then on triple or even quadruple patterning. Meanwhile, many studies have shown that it is very important to consider MPL implications at early physical design stages so that the overall design and manufacturing closure can be reached. In this paper, we provide a comprehensive overview on the state-of-the-art research results for MPL, from synergistic mask synthesis to physical design. We will also discuss the open problems as to pushing multiple patterning in sub-10nm.

This paper reviews the most critical components of a 'holistic' DTCO flow for an advanced technology node and in doing so quantifies the differences between 7nm technology node definitions implemented with extreme ultraviolet and 193nm immersion lithography. The DTCO topics covered include: setting scaling targets for critical pitches, gear-ratios, and cell height; defining a set of patterning solutions, required RET restrictions, and resulting patterning cost; compiling physical design objectives to achieve power, performance, and area scaling; developing a set of standard cell logic cell architectures; and finally assessing achievable cell-level as well as macro-level scaling.

A 10nm logic platform technology is presented for low power and high performance application with the tightest contacted poly pitch (CPP) of 64nm and metallization pitch of 48nm ever reported in the FinFET technology on both bulk and SOI substrate. A 0.053um2 SRAM bit-cell is reported with a corresponding Static Noise Margin (SNM) of 140mV at 0.75V. Intensive multi-patterning technology and various self-aligned processes have been developed with 193i lithography to overcome optical patterning limit. Multi-workfunction (WF) gate stack has been enabled to provide Vt tunability without the variability degradation induced by channel dopants.

In this paper, we present a 10nm CMOS platform technology for low power and high performance applications with the tightest contacted poly pitch (CPP) of 64nm and metallization pitch of 48nm ever reported in the FinFET technology on both bulk and SOI substrates. A 0.053um2 SRAM bit-cell is reported with a corresponding Static Noise Margin (SNM) of 140mV at 0.75V. Intensive multi-patterning technology and various self-aligned processes have been developed with 193i lithography to overcome optical patterning limits. Multi-workfunction (MWF) gate stack has been enabled to provide Vt tunability without the variability degradation induced by Random Dopant Fluctuation (RDF) from channel dopants.