With the industry moving to a disaggregated approach to constructing modern complex SoC designs, a large variety of digital, IO and PHY IP blocks are needed to be integrated on multiple advanced CMOS processes. Each IP on any given process node desires an optimal voltage to meet its performance and power efficiency goals. Delivering the aggregated sum of unique rails across all IPs, across die-stacks from the platform is extremely challenging, given the shrinking form factors of modern electronic systems. Furthermore, to maximize battery life, these IP blocks are actively lowering voltages, and are utilizing workload or activity-based supply voltages, like traditional DVFS, necessitating the need for localized voltage regulators (VR).

A monolithic buck voltage regulator (VR) built with top-metal and industry-first C4 planar spiral inductors demonstrates 2.5 times higher power density than prior art, providing efficient alternative to low-dropout linear regulators (LDOs) powering disaggregated digital, IO and PHY IPs. The 1.1 V single-stack power stage, DPWM delay-line, self-triggered windowed-flash ADC, and fully digital and reconfigurable controller are designed for high frequency, delivering 10.5 W/mm (2) at 600 MHz, with 0.35-0.85 V operating range and 18%-25% improvement in efficiency over an ideal LDO.

Circuit area scaling driven by Moore's law coupled with the push to thinner packages for mobile microprocessors has reduced the volume available for Air Core Inductors (ACI). This translates to a reduction in the conversion efficiency of Fully Integrated Voltage Regulator (FIVR). Magnetic Inductor Array (MIA) modules are used for the first time on the 10 th generation Intel Core™ microprocessor in mobile segments to improve FIVR efficiency. In addition to improving the peak efficiency, it is also possible to realize large light load efficiency gains and minimize voltage ripple through the use of magnetic inductors. This paper covers the magnetic inductor array (MIA) design considerations for improving performance as well as meeting high volume manufacturability and reliability requirements.

Intel fourth-generation and fifth-generation Core microprocessors are powered by high-frequency integrated switching voltage regulators. The inductors required to implement these regulators are constructed using the routing layers of conventional organic flip chip packaging. This paper provides an overview of the construction of these inductors including representative results from production packages. Measured inductors reported in this paper span from 1 to 6.7 nH under 2.4 mm(2) and achieve Q of up to 24 at 140 MHz (the switching frequency).

Intel® 4th generation Core™ microprocessors are powered by high frequency integrated switching voltage regulators. The inductors required to implement these regulators were constructed using the routing layers of conventional organic flip chip packaging. This paper provides an overview of the simulation and measurement of these embedded inductors including representative results from production packages.

This paper presents the design optimization work and its implementation in Intel's High Speed Telecommunication and Optical products in the Flip-Chip Molded Matrix Array Package (FCMMAP) packaging. The overall high speed modeling methodologies will be explained in this paper to describe electrical analysis work needed to identify the optimizations in the design. Specific substrate design attributes such as impedance matching, discontinuity and material losses will be presented. Validation results based on Intel's first high speed 40Gbps prototype will be published in this paper as well.

This paper investigates various options for 1st & 2nd level high-density interconnect technologies enabling next generation 10-20 Gbps/channel chip-to-chip link speed. In comparison to current technologies, the new technology options include thinner dielectric substrate, thinner copper for signal layer, lower loss dielectric material, Cu-alloy spring LGA (land-grid array) sockets, and conductive elastomer LGA sockets. In the evaluation of each technology, the modeling and validation methods are to be electrically accurate, mechanically stable and practically realizable. With these concepts in mind, various test coupons, measurements and modeling setups, and fixtures were designed to investigate various aspects of high-speed IO signal integrity impacted by different stack-ups, dielectric substrate materials and socket pin technologies. This paper highlighted some representative cases of modeling and validation methods specifically developed for Intel CPU chip-carrier packages and sockets.