This paper presents a comprehensive, system-level perspective on Intel’s development of Integrated Voltage Regulators (IVRs) enabling Vertical Power Delivery (VPD) for 5 kW AI accelerators. To realize high-density, high-efficiency power delivery, this work discusses three fundamental design pillars: advanced passive components, innovative circuit topologies and packaging, and leading-edge GaN technology featuring superior figures of merit (FoM). We review the implementation of ultra-dense Switched-Capacitor Voltage Regulators, including a 12.7 W/mm2 CSCR-First topology and a 91% peak-efficiency 4V Multistage Modular SCVR, that leverage Super High-Density MIM capacitors. Additionally, we examine a buck-based Fully Integrated Voltage Regulator design utilizing CoaxMIL inductors to overcome package-level z-height constraints. Finally, we provide a roadmap for high-voltage scaling using Intel's unique low-voltage GaN ICs. By uniting these three pillars, this work completes a highly scalable and complete framework for next-generation power delivery.

This paper presents a next-generation advanced packaging solution - Embedded multi-die interconnect bridge with through-silicon vias (EMIB-T), developed to meet the stringent bandwidth and power delivery requirements of cutting-edge HBM4E interfaces. The EMIB-T architecture incorporates a large number of metal layers, advanced routing capabilities, and integrated power delivery features. Wideband electrical measurements and modeling correlations validate the superior signal and power delivery performance of the technology. We further demonstrate signal integrity and power integrity optimizations for HBM4E integration with EMIB-T, confirming the feasibility of 12+ Gb/s operation, establishing EMIB-T as a cost-effective and scalable advanced packaging solution for ultra-large die complexes with HBM4E memory stacks.

AI boom in the past few years has increased the demand for compute, resulting in need for larger silicon content per package. Additionally, integration of high bandwidth memory (HBM), network and other I/O tiles necessitates the need for heterogenous integration using advanced packaging. Intel’s Embedded Multi-Die Interconnect Bridge (EMIB) with through silicon vias (TSVs) called EMIB-T provides a high bandwidth die-die and die-memory integration solution, with low power consumption, and the potential to scale to hyper large form factor (HLFF) package sizes (240 x 240 mm). This work describes the architectural considerations for designing packages up to the HLFF package sizes. Package constructions with two configurations are proposed incorporating Application Specific Integrated Circuit (ASIC), HBM and I/O dies. Architecture and IP considerations using EMIB-T for 2 configurations are described. Subsequently, high speed I/O (HSIO) considerations for necessary performance for ASIC-ASIC, die-HBM bandwidth, 448G Serializer/De-serializer (SerDes) data rates and off package communication is explained. Power delivery solutions to meet required power integrity (PI) is described with on-package power noise decoupling schemes and voltage regulator options. Yield modeling is leveraged to delineate redundancy solutions, demonstrating design for yield. Thermal and thermo-mechanical design considerations are proposed to mitigate warpage driven challenges. Lastly, future scope for HLFF and AI packages are proposed.

Intel Foundry’s Embedded Multi-die Interconnect Bridge with Through-silicon via (EMIB-T) technology [1] offers a scalable heterogeneous integration solution for chiplets because of its ability to combine the fine-pitch interconnect density of 2.5D integration with the vertical scaling benefits of through-silicon-via based architectures.In this paper, we will present the scaling of the EMIB-T technology, specifically scaling the First Layer Interconnect (FLI) bump pitch down to 25 um and the package form factor size up to > 120 mm x 120 mm, which enables hosting more than 9x reticles of compute and memory silicon content on a single package. We will illustrate the achievable bandwidth densities resulting from this technology scaling and demonstrate that the electrical characteristics of EMIB-T enable reliable high-speed signaling exceeding 12 Gb/s for HBM4e. Finally, we will share the roadmap to enable future capabilities and new functionalities of EMIB-T, which will allow architects and designers to build a complete system on a single package to meet the future HPC/AI demands.

CoaxMIL inductors are the latest package in-situ inductors with a high ratio of inductance to resistance for fully integrated voltage regulators (FIVRs). However, it is challenging to achieve both high efficiency and high density with CoaxMIL due to the fundamental performance trade-off of uncoupled inductors. This paper introduces a coupled package integrated coaxial magnetic inductor (CoaxMIL-C), which relieves the trade-off of CoaxMIL. By adding phase coupling to CoaxMIL structures, the proposed CoaxMIL-C reduces the inductor size by 33% and improves the transient performance while maintaining the efficiency of conventional CoaxMIL inductors. Performance is verified with lab measurements and validated with a FIVR test bench with external inductor pads. CoaxMIL-C provides 24 A/mm2 maximum density and enables the FIVR to achieve 89% peak efficiency at 1.75 V to 0.75 V conversion.

This application paper addresses the problem of transient simulation of system-level power distribution networks (PDNs) of multicore processing systems. In particular, we consider a postlayout power integrity (PI) verification problem where all system parts are finalized and a highly accurate transient verification is performed to ensure that voltage supply signals remain within prescribed bounds when the PDN is loaded by realistic current stimuli. Systems with tens of even hundreds of cores are considered, equipped with per-core local voltage stabilization, attained through integrated voltage regulators (IVRs) suitably controlled by sensing and feedback loops. Transient simulation of such system-level PDNs becomes particularly challenging when interconnect models or macromodels computed by electromagnetic solvers are embedded. In order to break system complexity, we propose a set of algorithms based on an ad hoc system partitioning strategy, combined with multilevel waveform relaxation (WR) schemes. The main advantage of this approach is a straightforward parallelization, aimed at solving concurrently by parallel computing threads only small and well-defined circuit partitions. Several partitioning and associated WR schemes are discussed and tested, showing excellent scalability with up to 60 computing threads, with significant speedup in runtime with respect to a standard SPICE-based approach.

This paper presents the industry’s first and only 48V, on-package, intermediate bus converter (IBC) solution with an 8:1 fixed ratio using low-voltage (LV) GaN power transistors with 10x superior figure of merit over Si laterally diffused MOS (LDMOS) for high performance computing applications. Eleven 2x2 mm GaN half-bridge dies along with the passives are co-packaged to form an 8:1 switched capacitor divider. This 1-MHz 200-W IBC prototype achieves a peak efficiency of 96.1% and a power density of 6.8 kW/in3.

Embedded multi-die interconnect bridge (EMIB) is a significant packaging technology platform currently in high-volume production, offering high-density, and localized in-package interconnects for the heterogeneous integration (HI) of chips. We describe initial success in expanding the EMIB technology envelope along four vectors i.e., pitch and wire scaling, addition of through silicon vias (TSVs) in the bridge, demonstration of an open cavity architecture, and the integration of active bridge die. All four technology vectors result in significant improvements in the HI envelope and will lead to significantly improved HI products.

This paper presents a 5.4V-V in , 0.6-1.8V V out , 10MHz LDMOS-based buck IVR chiplet implemented in a 55nm BCD process featuring a self-timed bootstrap technique and same-cycle all-digital ZVS control to achieve 9.3A/mm 2 current density and 93.6% peak conversion efficiency, while meeting all reliability constraints. The IVR chip supports a maximum load current of 80A and occupies 8.6mm 2 die area.

With the industry moving to a disaggregated approach to constructing modern complex SoC designs, a large variety of digital, IO and PHY IP blocks are needed to be integrated on multiple advanced CMOS processes. Each IP on any given process node desires an optimal voltage to meet its performance and power efficiency goals. Delivering the aggregated sum of unique rails across all IPs, across die-stacks from the platform is extremely challenging, given the shrinking form factors of modern electronic systems. Furthermore, to maximize battery life, these IP blocks are actively lowering voltages, and are utilizing workload or activity-based supply voltages, like traditional DVFS, necessitating the need for localized voltage regulators (VR).

A monolithic buck voltage regulator (VR) built with top-metal and industry-first C4 planar spiral inductors demonstrates 2.5 times higher power density than prior art, providing efficient alternative to low-dropout linear regulators (LDOs) powering disaggregated digital, IO and PHY IPs. The 1.1 V single-stack power stage, DPWM delay-line, self-triggered windowed-flash ADC, and fully digital and reconfigurable controller are designed for high frequency, delivering 10.5 W/mm (2) at 600 MHz, with 0.35-0.85 V operating range and 18%-25% improvement in efficiency over an ideal LDO.

This paper describes a novel control scheme for voltage regulators(VRs) with hybrid implementation of both coupled inductors and discrete inductor. The proposed control policy optimizes both output current ripple and inductor copper loss balance. Detailed theoretical analysis and simulation results demonstrate the effectiveness of the proposed scheme in extending the application of coupled inductor-based VRs to odd phase counts.

This paper proposes a comprehensive model order reduction framework to enable fast power integrity verification at the system level. This approach is developed to compress models of complete power delivery networks of high-end multiprocessor systems, where electromagnetic models of board and package are connected through banks of per-core Fully Integrated Voltage Regulators to chip models and loads in a closed-loop configuration. Due to complexity in both dynamical behavior and number of signals to be monitored, a direct transient simulation at the system level is very challenging. We show that a careful topological formulation of the circuit equations leads to a global model format that enables a structured projection framework for the elimination of the redundant states. Within this framework, we present and compare two alternative approaches based on approximate interpolation and empirical balancing, here adapted for the application at hand. In both cases, the resulting system is proven to be unconditionally stable both in open and in closed-loop configuration. Transient simulation of the reduced system provides a speedup exceeding $100\times $ with respect to SPICE.

Power demand on computing microprocessors has been increasing steadily, demanding more efficient high density power delivery solutions. This work introduces a next-generation package integrated coaxial magnetic integrated inductor (CoaxMIL) developed with a new magnetic material and improved plating technology for significantly higher performance power delivery over prior integrated inductors. The process of optimizing CoaxMIL is presented, followed by simulation and measurement results.

This paper presents the design and optimization of a miniaturized 48-V-to-1-V, 240-A linear-extendable group operated point-of-load (LEGO-PoL) CPU voltage regulation module (VRM) – Mini-LEGO – with a volume of 30 mm×11.2 mm×8.4 mm.The Mini-LEGO converter provides vertical power delivery, and it achieves a peak efficiency of 87.1%, a full load efficiency of 84.1%, and a power density of 1,390 W/in3 when stepping down a 48 V input voltage to an output voltage of 1 V. The Mini-LEGO offers compact device implementation, simple gate drive circuitry, and a fast regulation-stage switching frequency of 1.5 MHz. The 9-mmby-9-mm, 4-phase, 20-A-per-phase vertical coupled inductor has a per-phase transient inductance of 10.3 nH, with its coupling reducing the ripple by a factor of six, and a height of 2.5 mm. This vertical coupled inductor structure is designed following a systematic approach to minimizing its height while achieving significant current ripple reduction and maintaining sufficient saturation margin. Thermal simulations are performed to verify the cooling feasibility. A measurement characterization method for vertical coupled inductor structures is introduced and used to characterize the designed vertical coupled inductor.

This paper presents a model order reduction approach, specifically designed for the generation of compact and efficient transient simulation models of system-level power distribution networks (PDN) of multicore processor systems. The proposed approach applies a Krylov subspace projection, with a structure that is adapted to a block-coupled state-space description of individual PDN subsystems. The latter include board-package, averaged models of integrated voltage regulators switching circuitry, and individual models of all cores including regulator inductors and capacitors. Numerical results from pro-posed reduced-order models provide major speedup with respect to SPICE with negligible loss of accuracy.

This paper considers a complete power delivery network model of a multicore processing system, including per-core voltage regulation loops through Fully Integrated Voltage Regulators. Based on a nonlinear descriptor formulation of the system equations, we propose a transient solver based on a two-level Waveform Relaxation iteration. The convergence properties and the scalability of this solver when implemented on a parallel computing architecture are investigated. Numerical results show fast convergence and excellent scalability properties.

This paper presents a comprehensive overview of circuits and magnetics co-design for point-of-load voltage regulator modules (VRMs), which delivers power to microprocessors such as CPUs and GPUs that require low voltages and high currents. We examine the recent shift from the 12-volt to the 48-volt architecture to achieve higher efficiency and power density, and discuss the challenges associated with direct 48-volt power conversion to the point of load below 1 volt. Power delivery architectures for 48-volt VRMs are systematically reviewed and categorized, with emphasis placed the opportunities and challenges of circuits–magnetics co-design for energy efficiency, power density, and control bandwidth. Magnetic components, such as inductors and transformers, are essential components in VRMs, and a discussion on available materials and their limitations is provided. A comprehensive design approach for ultra-thin vertical multiphase coupled magnetics, including modeling magnetic core losses with machine learning, is detailed. This review paper aims to disseminate the progress and challenges in circuit and magnetics co-design, while outlining a vision for future advancements in device technology, magnetic materials, and packaging techniques including hybrid-switched-capacitor and coupled magnetics technologies.