The development of size- and shape-controlled nanomaterials is essential to tailor their properties and performance for wide-ranging applications from catalysis to sensing. Solid-state synthesis of nanostructures is attractive from a sustainability perspective, but they typically lack the desired size and shape control at small-scale dimensions. This work shows that colloidal precursors can be used in a solid-state route to form hybrid core-shell nanostructures with simultaneous size and morphology control. Encapsulation of PtNPs with a well-defined Cu2O shell produces CuPt@Cu2O core-shell nanocubes grown directly from the underlying substrate. The controlled formation of the nanostructures is facilitated by the diamine passivation layer on the Cu substrate. On-substrate growth of the nanocubes gives ease of postsynthesis processing for them to be used directly in electrochemical applications. We show that the synthesized nanostructured substrates have high sensitivity as an electrocatalyst for glucose sensing. We further demonstrate their potential for direct methanol fuel cells by assessing the methanol oxidation reaction (MOR). The mass activity is determined to be 1.656 A mgPt-1 for MOR, and initial studies indicate the substrates show high CO tolerance.

•The resistance to oxidation is dependent on the length of thiol chain•Oxidation resistance increases with increasing chain length.•Acceptable oxidation resistance down the C4 chain length.•Van der Waals interactions are significant for SAM stability.The use of self-assembled monolayers (SAMs) of heteroalkanes as passivation layers to protect against oxidation has been studied on a variety of materials. However, typically heteroalkanes with C8 and longer have been used, since the contributing van der Waals between the carbon chains is a significant stabilising force and the longer the chain the greater the force. The industry requirement for passivating semiconducting materials is that they remain oxide free for a queue time of 24 h. The remit of this study is to explore whether passivation using shorter chain alkanethiols, which would be beneficial for reducing carbon, will work to prevent re-oxidation over this time frame. A series of 1-alkanethiols, with chain lengths from C2 to C12 are used to create SAMs on Ge(100) and a study of the re-oxidation of the passivated Ge upon exposure to ambient conditions is undertaken in an effort to determine how chain length effects oxidation resistance of the passivated Ge. X-ray photoelectron spectroscopy is used, complimented by water contact angle measurements to show that the longer thiol molecules outperform their shorter-chain counterparts at inhibiting re-oxidation over 168 h of exposure to ambient. Nonetheless, Ge surfaces passivated by the short-chain thiols, down to C4, still display acceptable resistance to re-oxidation. Finally, a detailed summary of density functional theory simulations whereby the most stable SAM structures and coverages are explored.

Germanium is a critically important material for future complementary metal-oxide-semiconductor devices, however, to maximise its potential it is necessary to develop a robust passivation process that prevents Ge re-oxidation for a queue time of 24 h. Self-assembled monolayers (SAMs) of alkanethiols on Ge have previously been shown to inhibit oxidation; however, re-oxidation eventually occurs when exposed to ambient conditions. Herein, it is shown that humidity plays a key role in the degradation of the SAM, ultimately resulting in re-oxidation. To demonstrate this, thiol-passivated Ge(100) surfaces are exposed to controlled humidity environments with different levels of relative humidity (RH). The rate of re-oxidation of the Ge surfaces are tracked using X-ray photoelectron spectroscopy and water contact angle analysis to discern what role RH plays in the re-oxidation of the Ge and the degradation of the SAM passivation. Atomic force microscopy data is presented to show that humidity-mediated re-oxidation of the Ge has little or no impact on the route mean square roughness of those surfaces. Finally, atomistic modelling of thiol-SAM passivated Ge in the presence of water molecules has been studied using first principles density functional theory in order to simulate experimental conditions and to understand the atomic level processes that determine stability in hydrophilic and hydrophobic configurations.

Reported here is a new chemical route for the wet chemical functionalization of germanium (Ge), whereby arsanilic acid is covalently bound to a chlorine (Cl)-terminated surface. This new route is used to deliver high concentrations of arsenic (As) dopants to Ge, via monolayer doping (MLD). Doping, or the introduction of Group III or Group V impurity atoms into the crystal lattice of Group IV semiconductors, is essential to allow control over the electronic properties of the material to enable transistor devices to be switched on and off. MLD is a diffusion-based method for the introduction of these impurity atoms via surface-bound molecules, which offers a nondestructive alternative to ion implantation, the current industry doping standard, making it suitable for sub-10 nm structures. Ge, given its higher carrier mobilities, is a leading candidate to replace Si as the channel material in future devices. Combining the new chemical route with the existing MLD process yields active carrier concentrations of dopants (>1 × 1019 atoms/cm3) that rival those of ion implantation. It is shown that the dose of dopant delivered to Ge is also controllable by changing the size of the precursor molecule. X-ray photoelectron spectroscopy (XPS) data and density functional theory (DFT) calculations support the formation of a covalent bond between the arsanilic acid and the Cl-terminated Ge surface. Atomic force microscopy (AFM) indicates that the integrity of the surface is maintained throughout the chemical procedure, and electrochemical capacitance voltage (ECV) data shows a carrier concentration of 1.9 × 1019 atoms/cm3 corroborated by sheet resistance measurements.

Conformal damage-free doping is the holy grail for 3D semiconductor device structures, such as those used in multi-gate and nanowire-based field effect transistors (FETs). The shape, dimension, pitch, and spacing of parallel conduction paths introduce increased complexity in a number of ways, but particularly in the area of intentional impurity introduction for doping. To this end, gas-phase doping using tertiarybutylarsine (TBA) was employed to dope silicon-on-insulator (SOI) thin films based circular transfer length measurement (CTLM) devices with top silicon thicknesses down to 4.5 nm, and substrate-released horizontal Si nanowires. Dopant incorporation was observed with a peak active carrier concentration of similar to 7 x 10(19) cm(-3) after a 1050 degrees C rapid thermal anneal (RTA). An optimisation study showed that dopant incorporation is similar for varying exposure times to TBA gas, while increased exposure can cause roughening of the Si due to etching. Structural analysis by cross-sectional transmission electron microscopy (XTEM) and Energy-dispersive X-ray spectroscopy (EDX) showed conformal formation of an As-rich surface oxide on free standing nanowires, without surface etching or crystal damage, making this process promising for future gate-all-around (GAA) transistor architectures.

Continued scaling of electronic devices shows the need to incorporate high mobility alternatives to silicon, the cornerstone of the semiconductor industry, into modern field effect transistor (FET) devices. Germanium is well-poised to serve as the channel material in FET devices as it boasts an electron and hole mobility more than twice and four times that of Si, respectively. However, its unstable native oxide makes its passivation a crucial step toward its potential integration into future FETs. The International Roadmap for Devices and Systems (IRDS) predicts continued aggressive scaling not only of the device size but also of the pitch in nanowire arrays. The development of a vapor-phase chemical passivation technique will be required to prevent the collapse of these structures that can occur because of the surface tension and capillary forces that are experienced when tight-pitched nanowire arrays are processed via liquid-phase chemistry. Reported here is a vapor-phase process using hexanethiol for the passivation of planar Ge(100) substrates. Results benchmarking it against its well-established liquid-phase equivalent are also presented. X-ray photoelectron spectroscopy was used to monitor the effectiveness of the developed vapor-phase protocol, where the presence of oxide was monitored at 0, 24, and 168 h. Water contact angle measurements compliment these results by demonstrating an increase in hydrophobicity of the passivated substrates. Atomic force microscopy monitored the surface topology before and after processing to ensure the process does not cause roughening of the surface, which is critical to demonstrate suitability for nanostructures. It is shown that the 200 min vapor-phase passivation procedure generates stable, passivated surfaces with less roughness than the liquid-phase counterpart.

This paper presents the application of monolayer doping (MLD) to silicon-germanium (SiGe). This study was carried out for phosphorus dopants on wafers of epitaxially grown thin films of strained SiGe on silicon with varying concentrations of Ge (18%, 30%, and 60%). The challenge presented here is achieving dopant incorporation while minimizing strain relaxation. The impact of high temperature annealing on the formation of defects due to strain relaxation of these layers was qualitatively monitored by cross-sectional transmission electron microscopy and atomic force microscopy prior to choosing an anneal temperature for the MLD drive-in. Though the bulk SiGe wafers provided are stated to have 18%, 30%, and 60% Ge in the epitaxial SiGe layers, it does not necessarily mean that the surface stoichiometry is the same, and this may impact the reaction conditions. X-ray photoelectron spectroscopy (XPS) and angle-resolved XPS were carried out to compare the bulk and surface stoichiometry of SiGe to allow tailoring of the reaction conditions for chemical functionalization. Finally, dopant profiling was carried out by secondary ion mass spectrometry to determine the impurity concentrations achieved by MLD. It is evident from the results that phosphorus incorporation decreases for increasing mole fraction of Ge, when the rapid thermal annealing temperature is a fixed amount below the melting temperature of each alloy.

For the first time a combination of monolayer doping with RF plasma treatment was used for low-temperature doping of Si nanowires (NW). To study the doping effect, the back-gate MOSFET formed with Si nanowires fabricated in silicon-on-insulator wafers, was used. Employment of transfer IdVbg characteristics of the back-gate Si NW MOSFETs gives us a possibility to extract source-drain contact resistance, effective electron mobility in the Si NW channel, resistivity and an average doping concentration of the Si NW after RF plasma treatment. It was shown that using an RF plasma treatment with a specific power of (1.0+2.0) W/cm2 for 15 minutes, at which a sample temperature does not exceed 350°C allows imbedding of the dopant impurity in the Si NW up to an average concentration above 1×1017 cm-3.

Silicon (Si) has been scaled below 10 nm in multigate and silicon-on-insulator (SOI) device technologies, but clearly Si thickness cannot be reduced indefinitely, as we will run out of atoms eventually. As thickness approaches 5 nm, surfaces and interfaces will significantly impact the electrical behavior of Si, and surface physics cannot be discounted. Below that, bulk material properties will be altered considerably in the few-monolayer limit. One of the most basic defining properties of a semiconductor is its conductivity. To improve conductivity, while inducing a channel by appropriate biasing, it is necessary to define an accurate impurity doping strategy to reduce parasitic resistance. In this paper, we investigated the changing electrical conductivity of SOI films as a function of the Si thickness, in the range of 3–66 nm. SOI films were ex situ doped using three different approaches: liquid/vapor phase monolayer doping of phosphorus using allyldiphenylphosphine, gas-phase doping of arsenic using arsine (AsH3), and room-temperature beam-line ion implantation of phosphorus. The circular transfer length method and micro-four-point probe measurements were used to determine the resistivity of the Si films, mitigating the contribution from contact resistance. The resistivity of the Si films was observed to increase with decreasing Si film thickness below 20 nm, with a dramatic increase observed for a Si thickness at 4.5 nm. This may drastically impact the number of parallel conduction paths (i.e., nanowires) required in gate-all-around devices. Density functional theory modeling indicates that the surface of the Si film with a thickness of 4.5 nm is energetically more favorable for the dopant atom compared to the core of the film.

This paper details the application of phosphorus monolayer doping of silicon on insulator substrates. There have been no previous publications dedicated to the topic of MLD on SOI, which allows for the impact of reduced substrate dimensions to be probed. The doping was done through functionalization of the substrates with chemically bound allyldiphenylphosphine dopant molecules. Following functionalization, the samples were capped and annealed to enable the diffusion of dopant atoms into the substrate and their activation. Electrical and material characterisation was carried out to determine the impact of MLD on surface quality and activation results produced by the process. MLD has proven to be highly applicable to SOI substrates producing doping levels in excess of 1 × 1019 cm−3 with minimal impact on surface quality. Hall effect data proved that reducing SOI dimensions from 66 to 13 nm lead to an increase in carrier concentration values due to the reduced volume available to the dopant for diffusion. Dopant trapping was found at both Si–SiO2 interfaces and will be problematic when attempting to reach doping levels achieved by rival techniques.

Due to limitations of ion-beam implantation for thin-body and 3D device geometries, techniques that allow for strict control over dopant diffusion are required. Advanced and conformal doping technologies are key for the continued scaling of semiconductor device past sub-10-nm dimensions. Monolayer doping (MLD) has been shown to satisfy the requirements for conformal and controllable doping on many materials ranging from devices fabricated from silicon and germanium to emerging replacement materials such as III–V compounds. Despite the enormous progress in the last decade, challenges still remain, especially with regard to suitable single-atom characterization techniques, surface roughness characterization, and investigation of the role of carbon. This article concisely summarizes the monolayer-doping technique and its application to dope silicon-, germanium-, and III–V-based materials and nanostructures to obtain shallow diffusion depths coupled with high-carrier concentrations.

To maintain electron device scaling, in recent years the semiconductor industry has been forced to move from planar to non-planar thin-body electron device architectures. This alone has created the need to develop a radically new, non-destructive, conformal method for doping. Doping alters the electrical properties of a semiconductor, related to the access resistance. Monolayer doping (MLD) is a promising surface-based technique, whereby organic molecules are covalently bound to the semiconductor surface at relatively low processing temperatures (room temperature - 160 °C). A thermal treatment is then applied which both frees the dopant atoms from the organic molecules, and provides the energy for diffusion into the semiconductor substrate and subsequent activation. Very promising results have been achieved, but mostly on planar unpatterned substrates. There is now a need to assess the suitability of MLD for thin-body semiconductor features with high surface-to-volume ratios and densely packed structures. It is the aim of this review paper to consider MLD from this perspective.

Dopant incorporation in Si can be done in situ during epitaxial growth, or ex situ for localised material modification from a variety of sources including ion, solid, liquid, or gas. Gas-phase doping has the advantage that it does not require a thin film deposition, it is more effective at entering tight spaces than a liquid, and it is less damaging and more conformal than a beam-line ion implant. In this work, we apply arsine (AsH3) gas at approximately atmospheric pressures in order to n-type dope three-dimensional (3D) Si device structures. It was observed that the gas-phase doping can be either corrosive or gentle to thin-body Si depending on the process conditions. Initial doping processes caused damage to the Si due to etching, but after process optimisation, the structural integrity of the Si nanostructures could be maintained successfully. Moreover, it was noted that evaluating doping processes entirely on planar Si surfaces can be misleading: processes which appear promising initially may not be transferrable to non-planar thin-body structures like fins or nanowires, due to unwanted Si etching. Overall, we found that gas-phase doping with AsH3 could provide >1020 cm−3 electrically active As concentrations. This high As incorporation makes gas-phase doping very attractive for future gate-all-around devices, where the space between features will decline with continued transistor scaling.

Introduction of dopant impurities in Si can be done in-situ during epitaxial growth, or ex-situ for localized material modification using a variety of sources including ion implantation, solid, liquid, or gas. In this work, we apply these methods for dopant incorporation and evaluate their effectiveness via electrical characterization. Moreover, it should be noted that evaluating doping processes entirely on planar Si surfaces can be misleading: processes which appear promising initially may not be transferrable to non-planar, thin-body structures like fins or nanowires, due to undesirable effects such as unwanted etching of the Si, and the difficulty in accessing all surfaces of extremely finely-spaced features. Arrays of Si nanowires, with diameters between 10 and 300 nm, and with inter-wire separations ranging from 20 to 1000 nm are fabricated by e-beam lithography, doped using the various methods, then measured electrically to evaluate the effectiveness of each method with respect to wire diameter and spacing. Calculated values for the material resistivity (accounting for contact resistance and wire geometry) are used to benchmark each process. Dopant incorporation was also evaluated on planar silicon-on-insulator (SOI) substrates of different Si thickness, ranging from 3 to 66 nm electrical characterization. These measurements show the influence of silicon thickness and drop-off of the electrical performance as SOI is scaled down towards its ultimate limit.

The advent of high surface-to-volume ratio devices has necessitated a revised approach to parameter extraction and process evaluation in field-effect transistor technologies. In this work, active doping concentrations are extracted from the electrical analysis of Si nanowire devices with high surface-to-volume ratios. Nanowire resistance and Si resistivity are extracted, by first extracting and subtracting out the contact resistance. Resistivity (q) is selected as the benchmark parameter to compare different doping processes with each other. The impacts of nanowire diameter scaling to 10 nm and of nanowire spacing scaling to <20 nm are extracted for monolayer doping and beam-line ion implantation. Despite introducing significant crystal damage, P beam-line ion implantation beats allyldiphenylphosphine (ADP) P monolayer doping with a SiO2 cap in terms of lower Si resistivity and higher dopant activation, with dependencies on the nanowire width greater than on nanowire spacing. Limitations in ADP P monolayer doping with a SiO2 cap are due to the difficulties in dopant incorporation, as it is based on in-diffusion, and P atoms must overcome a potential barrier on the Si surface. Published by AIP Publishing.

Quantum confinement in a semimetal thin film such as bismuth (Bi) can lead to a semimetal-to-semiconductor transition which allows for the use of semimetals as semiconductors when patterned at nanoscale lengths. Bi native oxide on Bi thin film grown by molecular beam epitaxy (MBE) is investigated using X-ray photoelectron spectroscopy (XPS) to measure the elemental composition of the oxide. Also, an in-situ argon plasma etch step is developed allowing for the direct coating of the surface of thin Bi films by a metal contact to form a Schottky junction. Model structures of rhombohedral [111] and [110] bismuth thin films are found from density functional theory (DFT) calculations. The electronic structure of the model thin films is investigated using a GW correction and the formation of an energy band gap due to quantum confinement is found. Electrical characterization of the fabricated Bi-metal Schottky diode confirms a band gap opening in Bi thin film for a film thickness of approximately 5 nm consistent with the theoretical calculations.

Bismuth has been identified as a material of interest for electronic applications due to its extremely high electron mobility and quantum confinement effects observed at nanoscale dimensions. However, it is also the case that Bi nanostructures are readily oxidised in ambient air, necessitating additional capping steps to prevent surface re-oxidation, thus limiting the processing potential of this material. This article describes an oxide removal and surface stabilization method performed on molecular beam epitaxy (MBE) grown bismuth thin-films using ambient air wet-chemistry. Alkanethiol molecules were used to dissolve the readily formed bismuth oxides through a catalytic reaction; the bare surface was then reacted with the free thiols to form an organic layer which showed resistance to complete reoxidation for up to 10 days.

This paper describes molecular layer doping of Ge nanowires. Molecules containing dopant atoms are chemically bound to a germanium surface. Subsequent annealing enables the dopant atoms from the surface bound molecules to diffuse into the underlying substrate. Electrical and material characterization was carried out, including an assessment of the Ge surface, carrier concentrations and crystal quality. Significantly, the intrinsic resistance of Ge nanowires with widths down to 30 nm, doped using MLD, was found to decrease by several orders of magnitude.

This article describes for the first time the controlled monolayer doping (MLD) of bulk and nanostructured crystalline silicon with As at concentrations approaching 2 × 10(20) atoms cm(-3). Characterization of doped structures after the MLD process confirmed that they remained defect- and damage-free, with no indication of increased roughness or a change in morphology. Electrical characterization of the doped substrates and nanowire test structures allowed determination of resistivity, sheet resistance, and active doping levels. Extremely high As-doped Si substrates and nanowire devices could be obtained and controlled using specific capping and annealing steps. Significantly, the As-doped nanowires exhibited resistances several orders of magnitude lower than the predoped materials.