The rush for better-performing electronics, and manufacturing processes that heavily rely on "top-down" patterning techniques, is making the integration of "self-aligned" fabrication methods, such as area-selective deposition (ASD), a critical objective for continued device scaling. The fully self-aligned via (FSAV) scheme is broadly proposed as a "killer application" to determine whether ASD can shift from an R&D process to high-volume manufacturing. Nevertheless, the lack of a suitable low-κ deposition process has prevented the realization of FSAV by dielectric-on-dielectric ASD. This is primarily due to the high temperature and/or strong oxidizers employed during low-κ dielectric deposition and their unsuitability in the presence of organic masks, such as self-assembled monolayers (SAMs), used to prevent material nucleation during ASD. In this work, AlOx and Al-silicate atomic layer deposition (ALD) processes are studied to provide suitable materials for ASD-enabled FSAV. Dimethylaluminum isopropoxide and H2O are utilized to deposit the metal oxide, whereas Al-silicate is grown by adding 2,2-dimethoxy-1,6-diaza-2-silacyclooctane (DMDAcO) pulses to the AlOx ALD cycle. The selectivity of such processes is demonstrated on 50 nm Cu/SiO2 structures, using octadecanethiol-derived SAMs to inhibit material nucleation on the metal lines. Scanning and transmission electron microscopies are employed to assess the quality of the ASD processes and investigate the mechanisms behind defect generation on a nongrowth surface. X-ray photoelectron spectroscopy measurements show the high purity of the AlOx film, whereas DMDAcO-ligand incorporation into the Al-silicate matrix is observed. Planar capacitor structures are used to assess the electrical properties of both ASD films, revealing that the silicate film exhibits a relatively low κ-value (5.3 ± 0.2), with a high acceleration field factor (32.4 ± 1.4) and a dielectric breakdown voltage of 6.0 ± 0.3 V at 100 °C.

We demonstrate that the retention of IGZO-based 2T0C devices is boosted by patterning the active module by RIE. While IBE generates Al redeposition on the device sidewalls creating an extrinsic conductive path, RIE enables a clean process which suppresses metal redeposition. With RIE, we achieve the lowest $\mathrm{I}_{\mathrm{O}\mathrm{F}\mathrm{F}}$ ever reported for 2T0C cells (<3× 1$0^{-21}$A/$\mu$m), and we successfully perform multi-level and multiply-accumulate operations enabling machine-learning applications. We also demonstrate device functionality down to $\mathrm{L}_{\mathrm{G}}$=25nm.

Area-selective deposition (ASD), a "bottom-up" substrate-selective material deposition process, is a promising solution to overcome the current limitations experienced in semiconductor manufacturing processes, which rely on "top-down" patterning techniques. To achieve this selective material growth, atomic layer deposition (ALD) is frequently employed in conjunction with a blocking layer to suppress material nucleation on the nongrowth areas. ASD is suitable on many levels of wafer manufacturing; notably, its "bottom-up" nature makes it more impactful at the smallest critical dimensions (CDs), such as sub-10 nm. Nevertheless, the ASD studies at such relevant nanoscale dimensions are very limited or nonexistent. Therefore, we studied ASD enabled by 1-octadecanethiol (ODT)-derived self-assembled monolayer (SAM) passivation on unprecedented scaled-down Cu/SiO2 patterns, targeting ASD of hafnium nitride on 10 nm-wide dielectric spacings. Pulsed force atomic force microscopy nanomechanical characterization proved the tight confinement of the organic layer to the metal lines even on such high-density patterns. In addition, transmission electron microscopy, energy-dispersive X-ray spectroscopy, and scanning electron microscopy (SEM) measurements reveal the selective and conformal deposition of similar to 5.0 nm hafnium nitride film on the 10 nm-wide SiO2 spacings. Nevertheless, it is shown that, as the pattern features shrink, the undesired lateral expansion of the isotropically growing ALD film becomes a more stringent limitation to the ASD resolution. The "monolayer trade-off" associated with the employed passivation to enable ASD is analyzed in this work. In fact, a monolayer-thick blocking film is desired to avoid poisoning of the growth surface, whereas the ASD film lateral expansion could be effectively prevented if thicker passivation films are employed instead.

In this paper, the kinetics of Ni metal induced lateral crystallization (MILC) in a Si channel has been thoroughly investigated. The impact of excess Ni supply, high-and-long thermal treatments, and fast ramp rate annealing on the quality of Si channel formed are reported. We show that it is possible to achieve up to 10 times higher mobility, and enhanced channel control with a controlled MILC process compared to a regular polysilicon channel.

The deep levels in amorphous Ge0.5Se0.5 layers have been analyzed by Deep Level Transient Spectroscopy (DLTS). To that end, Metal-Insulator-Semiconductor (MIS) capacitors have been prepared by Physical Vapor Deposition of the films on p-type silicon substrates. A so-called quasi-constant capacitance procedure has been developed to account for the strong flat-band voltage shift of the capacitance-voltage characteristic with temperature. Applying this procedure to the as-deposited layers in the subthreshold regime reveals a dominant broad hole trap, with deep level parameters (trap concentration, hole capture cross section and activation energy) that strongly depend on the deposition conditions and the layer thickness. It is, finally, shown that the trap filling behavior does not follow the capture kinetics for simple point defects. Based on this observation, arguments are presented for an alternative analysis of the DLTS data. (C) 2020 The Electrochemical Society ("ECS"). Published on behalf of ECS by IOP Publishing Limited.

The electrical activity of extended defects in III-V materials, combining different analysis methods based on lifetime extraction from diode current-voltage characteristics, time resolved photoluminescence (TRPL) and deep level studies using Deep Level Transient Spectroscopy (DLTS) is reviewed. To that purpose p(+)n junction diodes have been fabricated in In0.53Ga0.47As hetero-epitaxial layers on semi-insulating InP or GaAs substrates. By depositing a strained buffer layer, the Extended Defect Density (EDD) can be varied over several decades, enabling a systematic study of their electrical impact in the same range. The defect densities are determined by High-Resolution X-ray Diffraction (HR-XRD), DLTS and Electron Channeling Contrast (ECCI) techniques. The generation and recombination (GR) lifetimes of the In0.53Ga0.47As layers become dominated by the EDs for densities above about 3 x 10(7) cm(-2), whereby the dominant GR level moves closer to the mid gap position. This is supported by DLTS investigations, showing the occurrence of specific electron traps for defective epi layers, which exhibit a capture behavior that is typical for extended defects.

The electrical activity of extended defects in III-V materials, combining different analysis methods based on lifetime extraction from diode current-voltage characteristics, time resolved photoluminescence (TRPL) and deep level studies using Deep Level Transient Spectroscopy (DLTS) is reviewed. To that purpose p(+)n junction diodes have been fabricated in In0.53Ga0.47As hetero-epitaxial layers on semi-insulating InP or GaAs substrates. By depositing a strained buffer layer, the Extended Defect Density (EDD) can be varied over several decades, enabling a systematic study of their electrical impact in the same range. The defect densities are determined by High-Resolution X-ray Diffraction (HR-XRD), DLTS and Electron Channeling Contrast (ECCI) techniques. The generation and recombination (GR) lifetimes of the In0.53Ga0.47As layers become dominated by the EDs for densities above about 3 x 10(7) cm(-2), whereby the dominant GR level moves closer to the mid gap position. This is supported by DLTS investigations, showing the occurrence of specific electron traps for defective epi layers, which exhibit a capture behavior that is typical for extended defects. (C) 2020 The Electrochemical Society ("ECS"). Published on behalf of ECS by IOP Publishing Limited.

We present in this paper the use of Gas Source Molecular Beam Epitaxy for the large-scale growth of transition metal dichalcogenides. Fiber-textured MoS2 co-deposited thin films (down to 1 MLs) are grown on commercially 200 mm wafer size templates where MX2 crystalline layers are achieved at temperatures ranging from RT to 550 °C. Raman Spectroscopy and photoluminescence measurements along with X-Ray Photoelectron Spectroscopy show that a low growth rate is essential for complete Mo sulfurization during MoS2 co-deposition. Finally, cross-section Transmission Electron Microscopy investigations are discussed to highlight the influence of SiO2 and Al2O3 used surfaces on MoS2 deposition.

In the manufacturing of multi-Vt FinFET transistors, the gate material deposited in the nano-spaces left by the removed dummy gate must be etched back in mask-defined wafer areas. Etch conformality is a necessary condition for the control of under-etch at the boundary between areas defined by masking. We studied the feasibility of TiN etching by APM (ammonia peroxide mixture, also known as SC1) in nano-confined volumes representative of FinFET transistors of the 7 nm node and below, namely nanotrenches with 1-D confinement and nanoholes with 2-D confinement. TiN etching was characterized for rate and conformality using different electron microscopy techniques. Etching in closed nanotrenches was conformal, starting and progressing all along the 2-D seam, with a rate that was 38% higher compared to a planar film. Etching in closed nanoholes proved also to be conformal and faster than planar films, but with a delay to open the 1-D seam that seemed to depend strongly on small variations in the hole diameter. However, holes between the fins at the bottom of the removed dummy gate, are not circular and do present 2-D seams that should lend themselves for an easier start of conformal etching as compared to the circular nanoholes used in this study. Finally, to explain the higher etch rate observed in nano-confined features, concentrations of ions in nanoholes were calculated taking the overlap of electrostatic double layers (EDL) into account. With negatively charged TiN walls, as measured by streaming potential on planar films, ammonium was the dominant ion in nanoholes. As no chemical reaction proposed in the literature for TiN etching matched with this finding, we proposed that the formation of ammine complexes, dissolving the formed Ti oxide, was the rate-determining step.

This paper describes molecular layer doping of Ge nanowires. Molecules containing dopant atoms are chemically bound to a germanium surface. Subsequent annealing enables the dopant atoms from the surface bound molecules to diffuse into the underlying substrate. Electrical and material characterization was carried out, including an assessment of the Ge surface, carrier concentrations and crystal quality. Significantly, the intrinsic resistance of Ge nanowires with widths down to 30 nm, doped using MLD, was found to decrease by several orders of magnitude.

Due to the performance and economic benefit obtained by scaling, future semiconductor electron devices for logic functions will progress toward ultra-thin-body channels and 2-dimensional (2D) high carrier mobility materials. The significance is that small devices can be made to yield higher performance and greater energy-efficiency. To put this trend in perspective, fin-field-effect-transistor[i],[ii] (FinFET) technology was a research topic 7-8 years ago, but is now at the heart of the microprocessor in high-end smartphones.[iii] While the positioning of TMDs in electronic products of the future is still unsure, perhaps they will be more suited to low power, it is still worthwhile to understand how a relatively undeveloped system can reach maturity in less than a decade. Graphene is semi-metallic, which makes it difficult to switch off electron devices such as FETs. Bandgap engineering is required to open a bandgap of graphene, which is not an easy undertaking. This has motivated the scientific community to search for alternate 2D layer materials with semiconducting properties and better tuneability. Many TMDs are natural semiconductors with thicknesses on the nanometre scale. TMD semiconductors are now emerging as potentially useful materials, where more research is needed, in order to explore their properties and potential applications. Large-area synthesis is of great demand for the preparation of high-performance transition-metal-dichalcogenides (TMD) devices, however reports of device operation on large-area TMDs are sparse. In this work we fabricate MoS2 devices based on Thermal Assisted Conversion (TAC) of metal layers, and characterise the thin-films with material analysis combined with electrical device parameter extraction. Specifically we perform parameter extraction for MoS2 thin-films to determine sheet resistance (Rsh), resistivity (ρ), and activation energy (EA) of on-state current flow. For undoped MoS2, ρ was determined to be 191 Ω.cm at 25 °C. EA of the on-state current found to be 0.18 eV, points to a current generation mechanism possibly linked to a deep level in MoS2. In Fig. 1 are representative images of the 10 nm sulphurised Mo, forming approximately 20 nm of MoS2. In (a) a wide view of MoS2 on a SiO2/Si substrate. On the right-hand side the Ti/Au metal contact is visible. The MoS2 layer is continuous across the surface. In (b) the layered structure of MoS2 is visible in the higher resolution image. In Fig. 2 are representative measured current versus voltage characteristic in the MoS2 circular Transfer Length Method structure as a function of contact spacing. The current is linear with respect to voltage and passes through the origin. The current increases with decreased contact spacing as expected. The inset shows an optical images of the circular TLM structure. : [i] J. –P. Colinge (Ed.), “FinFETs and other Multi-Gate Transistors” ISBN 978-0-387-71752-4, Springer (2008). [ii] N. Collaert (Ed.), “CMOS Nanoelectronics: Innovative Devices, Architectures, and Applications” ISBN 9789814364027, Pan Stanford (2012). [iii] J. Borland, ECS Transactions, 69 (10) 11-20 (2015). Figure 1

Naturally super-latticed Aurivillius phase ferroelectrics can accommodate various magnetic ions, opening up the possibility of making new room temperature multiferroics.

Bismuth ferrite (BiFeO3) is a widely studied material due to its interesting multiferroic properties.Bismuth selflimiting growth pure, single-phase of BiFeO3 (BFO) has previously been achieved using molecular beam epitaxy (MBE), but the growth of BFO by chemical vapour deposition (CVD) has proved to be very challenging, due to the volatile nature of bismuth.The growth window regarding temperature, pressure and precursor flow rates that will give a pure perovskite BFO phase is normally very small.In this work we have studied the metal-organic CVD (MOCVD) growth of epitaxial BFO thin films on SrTiO3 substrates and found that by carefully controlling the amount of the iron precursor, Fe(thd)3, where thd = 2,2,6,6 tetra methyl 3,5 heptanedionate, we were able to achieve bismuth self-liming growth, for the first time.The effect of the volume of the bismuth and iron precursors injected on the growth of BFO thin films is reported and it has been found that the phase-pure films can be prepared when the Bi/Fe ratios are between 1.33 and 1.81 at temperature and pressure conditions of 650°C and 10 mbar respectively and where the O2 gas flow was kept constant to 1000sccm out of 3000sccm total gas flow.Piezoresponse force microscopy (PFM) studies demonstrate the presence of bipolar-switching in ultra-thin BFO films.

Metal insulator metal (MIM) capacitors are fundamental components of the electronic circuitry commonly found in many devices in areas such as analogue to digital conversion, micro-electromechanical systems, medical, automotive and memory applications [1-4]. Current MIMCAPS generally employ optimised low dielectric constant (k) materials (k~3.9 - 7) to attain the target electrical properties of high breakdown field and low current leakage. However, device scaling is limited due to the low k value of these materials and this presents a significant challenge to the future development of these technologies [5]. Many high k materials are under investigation to replace these lower k dielectrics to substantially increase the maximum capacitance density and reduce the area associated with the integration of MIM structures. In this work we investigate the growth of hafnium silicate films by plasma assisted atomic layer deposition on a metal electrode. The hafnium silicate film was deposited using Tetrakis(dimethylamino)hafnium (TDMAHf) and Tetrakis(dimethylamino)silane (TDMASi) precursors at 250oC with a remote oxygen plasma (300 W). From HR-TEM analysis and Raman spectroscopy it has been observed that the main crystalline phase is monoclinic HfO2. This crystallographic phase appears to be templated by the underlying titanium adhesion (10 nm) layer through the platinum electrode (200 nm). The HR TEM analysis also reveals the presence of nanoparticles, located primarily towards the lower platinum metal layer. Based on electron energy loss spectroscopy (EELS) analysis the nanoparticles are consistent with silicon oxide inclusions, located at HfO2 grain boundaries. In addition, the presence of additional phases was detected; these included a super-cell structure within the bulk and an amorphous phase. No hysteresis was observed in the capacitance voltage measurements and the material was observed to exhibit a k value of ~18. References [1] C. Zhu et al., IEDM Tech. Dig., 879–882 (2003). [2] S. J. Kim et al., IEEE Elec. Dev. Lett., 25 (8), 538–540 (2006). [3] F. El Kamel et al., Appl. Phys. Lett., 91 (17), 172 909 (2007). [4] A. Hastings, “The Art of Analog Layout”, Prentice Hall, New Jersey, 2001. [5] C. H. Ng et al., IEEE Elec. Dev. Lett. 24 (8), 506 (2003).

A design of experiments methodology was used to optimize the sheet resistance of titanium nitride (TiN) films produced by plasma-enhanced atomic layer deposition (PE-ALD) using a tetrakis(dimethylamino)titanium precursor in a N2/H2 plasma at low temperature (250 °C). At fixed chamber pressure (300 mTorr) and plasma power (300 W), the plasma duration and N2 flow rate were the most significant factors. The lowest sheet resistance values (163 Ω/sq. for a 20 nm TiN film) were obtained using plasma durations ∼40 s, N2 flow rates >60 standard cubic centimeters per minute, and purge times ∼60 s. Time of flight secondary ion mass spectroscopy data revealed reduced levels of carbon contaminants in the TiN films with lowest sheet resistance (163 Ω/sq.), compared to films with higher sheet resistance (400–600 Ω/sq.) while transmission electron microscopy data showed a higher density of nanocrystallites in the low-resistance films. Further significant reductions in sheet resistance, from 163 Ω/sq. to 70 Ω/sq. for a 20 nm TiN film (corresponding resistivity ∼145 μΩ·cm), were achieved by addition of a postcycle Ar/N2 plasma step in the PE-ALD process.

The geophysical uplift of broadband data is widely reported as are the benefits it brings to reservoir characterisation. However there are also benefits to the qualitative interpreter which go beyond improved resolution and structural imaging. In addition to the benefits to efficiency and accuracy whilst auto-picking, the manual interpreter can gather more geological information from the texture within the data than just having improved confidence in the structural and stratigraphic image. The broad bandwidth of frequencies within the data produce a texture to the data which can highlight geological packages which may have been previously masked within conventional data. There is geological understanding and information which may be inferred and when accurately tied to well information can increase confidence in model building and help to focus further quantitative interpretation.