Wepropose an integratedcontact mechanics and density-step-heightmodel of pattern dependencies for the chemical-mechanical polishing (CMP) of multi-level copper interconnects, and show preliminary comparisons with experimental data for the overburden copper removal stage. The model uses contact mechanics to correctly apportion polishing pressure on all sections of an envelop function that reflects the long-range thickness differences on the chip, or region of interest. With the pressure over the entire envelop known, the density-step-height part of the model is then used to compute the amount of material removed in the local “up-areas” and “down-areas”. ThismodelshowspromiseinaccuratelyandefficientlypredictingpostCMPcopperanddielectric thicknesses across an entire chip.

As the demand for planarity increases with advanced IC technologies, nanotopography has arisen as an important concern in shallow trench isolation (STI) chemical mechanical polishing (CMP) processes. Previous work has shown that nanotopography, or small surface height variations on raw wafers 20 to 50 nm in amplitude extending across millimeter scale lateral distances, can result in substantial CMP-induced localized thinning of surface films such as oxides or nitrides used in STI [1]. This interaction with CMP depends both on characteristics of the wafer such as heights and spatial wavelengths of the nanotopography, and characteristics of the CMP process including the planarization length or pad stiffness. In this paper we review and extend the previous work on modeling of nanotopography. Three approaches to predicting the post-CMP oxide thinning due to nanotopography are compared. The first approach is the simplest, where a statistical aggregate effect is computed. Following the work of Schmolke [2], a transfer coefficient α is found which captures the portion of the nanotopography that is correlated with the final oxide thinning. The second approach is the most detailed, depending on explicit numerical simulation of pad elastic properties. In this case, a contact wear simulation is used to produce a detailed map of oxide thickness corresponding to any given pre-measured nanotopography wafer surface. The third approach is a signal processing method, sitting somewhere between the previous two extremes in terms of approximation and complexity. In this last case, a two-dimensional transfer function is extracted which captures the spatial smoothing accomplished by CMP. This filter can then be applied efficiently to premeasured nanotopography maps for other wafers to predict the final oxide thicknesses. We also propose a predictive mapping of post-CMP oxide or nitride thicknesses to provide insight into the relative goodness of a wafer measured for nanotopography which is to be subjected to a CMP process. Specifically, we suggest that for post-CMP impact, maps and computation of areas having insufficient oxide clearing, or having final nitride thickness outside of required ranges, are useful and practical. Such device failure potential maps complement the fundamental nanotopography height map data and metrics based directly on that data, and enable evaluation, comparison, and development of improved wafers and STI CMP processes.

Nanotopography refers to 10-100 nm surface height variations that exist on a lateral millimeter length scale on unpatterned silicon wafers. Chemical mechanical polishing (CMP) of deposited or grown films (e.g., oxide or nitride) on such wafers can generate undesirable film thinning which can be of substantial concern in shallow trench isolation (STI) manufacturability. Proper simulation of the effect of nanotopography on post-CMP film thickness is needed to help in the measurement, analysis, diagnosis, and correction of potential problems. Our previous work has focused on modeling approaches that seek to capture the thinning and post-CMP film thickness variation that results from nanotopography, using different modeling approaches. The importance of relative length scale of the CMP process used (planarization length) to the length scale of the nanotopography on the wafer (nanotopography length) has been suggested. In this work, we report on extensive experiments using sets of 200 mm epi wafers with a variety of nanotopography signatures (i.e., different nanotopography lengths), and CMP processes of various planarization lengths. Experimental results indicate a clear relationship between the relative scales of planarization length and nanotopography length: when the planarization length is less than the nanotopography length, little thinning occurs; when the CMP process has a larger planarization length, surface height variations are transferred into thin film thickness variations. In addition to presenting these experimental results, modeling of the nanotopography effect on dielectric CMP processes is reviewed, and measurement data from the experiments are compared to model predictions. Results show a good correlation between the model prediction and the experimental data.

Our group has proposed several chip-scale CMP models, with key assumptions including the notion of planarization length in the pattern density model [1], and step height dependent polishing rate in the density step height model [2]. In the effective density model, planarization length is the characteristic length of an elliptic weighting function based on the long-range pad deformation and pressure distribution during CMP. This semi-physical model is often adequate and usually gives a fitting error of a few hundred angstroms. As ever-shrinking device size pushes for tighter control of post CMP uniformity, however, we need a chip-scale CMP model with better accuracy. In this work, we re-examine the physical basis for averaging weighting functions and step height dependence, particularly in the context of contact mechanics based model formulations. The comparison of the two models confirms that the analytical density and step height models can be viewed as approximations to the contact wear model. The study also suggests a new dependence of contact height on line space and pattern density.

In this paper, we introduce a mathematical model for chemical mechanical polishing (CMP) of reverse tone etchback shallow trench isolation (STI) structures. We present a detailed formulation of the model and describe CMP experiments using a newly designed STI CMP characterization mask to validate the model. A methodology for extracting the model parameters is also proposed. An improved modeling methodology that incorporates density averaging effects fits the experimental data more accurately. Finally, we use the model to predict the effects of pre-CMP step height, pattern density, polish time, pad hardness, and slurry selectivity on dishing and nitride erosion. (C) 2001 The Electrochemical Society. All rights reserved.

We present a density-step-height based pattern dependent model for abrasive-free chemical mechanical polishing (CMP) processes, and show comparisons with experimenta The model uses Hooke’s law to establish a mathematical relationship between effective pol pressure and step height. It uses this dependence together with the empirical relationship b the removal rate and the polishing pressure, to construct removal rate diagrams for the pr From these diagrams, equations for dishing and erosion, as functions of polish time and patterns can be derived. We also discuss the limitations of the model, and propose extensi overcoming them. Introduction In conventional copper CMP processes, polymeric polishing pads, and slurries containing or alumina abrasives are used. These polishing processes lead to dishing and erosion tha excessive when significant overpolishing is done [1-3]. To reduce these pattern depe problems, abrasive-free copper CMP processes are currently being developed, and preli results show great promise [4 6]. Abrasive-free copper CMP processes use the same po pads and polishing machines used in conventional copper CMP processes. However, th slurries that contain no abrasive particles, unlike those used in conventional copper processes. An example of an abrasive-free slurry is the Hitachi C430-1 [4 6]. Abrasive-free copper CMP processes are typically non-Prestonian in nature, with respect polishing of copper. This means that the copper removal rate does not vary linearly wit polishing pressure. Hence, all copper CMP models developed on the basis of Preston’s eq do not necessarily apply to abrasive-free copper CMP processes. In this paper, we pres first model of pattern dependencies in abrasive-free copper CMP processes. Copper CMP processes, prestonian or otherwise, comprise three intrinsic stages: bulk removal, barrier removal, and overpolishing [1]. The key to modeling abrasive-free copper processes is to first establish a mathematical relationship between removal rate and po pressure for a given relative speed, consumable set and slurry flow rate. This relationship used together with the Hooke’s law based pressure versus step height (or dishing) relation construct removal rate diagrams in each intrinsic stage of the polishing process. Remov diagrams are plots of removal rates versus step height or dishing. From these diagrams, formulate equations for the bulk copper thickness evolution, the bulk copper clearing time barrier clearing time, and the amounts of dishing and erosion. g the e die. ing of nd on r goal e and CMP ian in

Chemical mechanical polishing (CMP) has emerged as the planarization technique of choice in both front-end (STI) and back-end (ILD) integrated circuit manufacturing. Conventional CMP processes utilize a polyurethane polishing pad and liquid chemical slurry containing abrasive particles. More recent work has examined the use of a fixed abrasive CMP pad [1], in which abrasive material is embedded into the polishing pad and released during the polish. In this work, we present a closed form fixed abrasive CMP model derived using step-height and fixed abrasivespecific pattern density dependencies. We then propose a methodology for characterization and calibration of the model, and compared the model prediction to experimental data.

Chemical mechanical polishing (CMP) has become the preferred planarization method for multilevel interconnect technology due to its ability to achieve a high degree of feature level planarity. However, methods are needed to understand and model both wafer level and die level uniformity in interlevel dielectric (oxide) polishing. This paper examines the variation of die level planarity across the wafer and at different process conditions. Substantial dependency of planarization length, a characteristic length which determines die level planarity, on table speed and down pressure is found, varying from 6.2 to 7.8 mm in the experiments considered here. In addition, a dependence of planarization length on die position within the wafer is found, varying by similar to0.5 mm across the wafer resulting in a difference of similar to 300 Angstrom total indicated range from one die to the next. Some die are impacted even more strongly resulting in much smaller planarization lengths (near 5.0 mm in some cases) due to wafer edge effects. We conclude that accurate modeling and optimization of within-die variation depends on accurate modeling and measurement of not only wafer scale removal rate variation but also wafer scale planarization length variation. (C) 2000 The Electrochemical Society. S0013-4651(00)04-093-3. All rights reserved.

Plasma immersion ion implantation (PIII) has been developed as an alternative deep trench capacitor buried-plate doping technology and compared to a conventional solid-state diffusion technique using arsenosilicate glass (ASG). Novel top-down (or vertical) SIMS measurements demonstrated the conformal doping capability of PIII along the trench sidewall. The doping level by PIII was almost one order of magnitude higher than that by a conventional technique. As a consequence, PIII provided better depletion characteristics than conventional technique. Furthermore, PIII processing did not degrade node-to-buried plate leakage current characteristics. From these results, it was demonstrated that PIII is a promising technology as an alternative deep trench capacitor buried-plate doping technique for future deep trench-based DRAM processing development

A new set of wafer-scale patterns has been designed for analysis and modeling of key CMP effects. In particular, the goal of this work is to develop methods to characterize the planarization capability of a CMP process using simple measurements on wafer scale patterns. We examine means to pattern large trenches (e.g. 1 to 15 mm wide and 15 mm tall) or circles across 4” and 8” wafers, and present oxide polish results using both stacked and solo pads in conventional polish processes. We find that large separation (15 mm) between trenches enables cleaner measurement and analysis. Examination of oxide removal in the center of the trench as a function of trench width shows a saturation at a length comparable to the planarization length extracted from earlier studies of small-scale oxide patterns. Increase in polish pressure is observed to decrease this saturation point. Such wafer scale patterns may provide information on pad flexing limits in addition to planarization length, and promise to be useful in both patterned wafer CMP modeling and studies of wafer scale CMP dependencies such as nanotopography.

The techniques of dummy fill and reverse etchback are often used prior to a chemical mechanical polishing (CMP) process to prevent film pattern density mismatches that lead to post-CMP film thickness variation. In this work, we present a methodology that utilizes both techniques in an intelligent fashion, and shows that both techniques can be used together to create a better balance of pattern densities than each technique can do separately. We introduce the idea of a selective reverse etchback method to lower the pattern density in high density regions, and smart dummy fill to raise pattern densities in low density regions. We then verify the methodology on the STI active area layer of a test mask.

In previous work, we have formalized the notions of “planarization length” and “planarization response function” as key parameters that characterize a given CMP consumable set and process. Once extracted through experiments using carefully designed characterization mask sets, these parameters can be used to predict polish performance in CMP for arbitrary product layouts. The methodology has proven effective at predicting oxide interlevel dielectric planarization results. In this work, we discuss extensions of layout pattern dependent CMP modeling. These improvements include integrated up and down area polish modeling; this is needed to account for both density dependent effects, and step height limits or step height perturbations on the density model. Second, we discuss applications of the model to process optimization, process control (e.g. feedback compensation of equipment drifts), and shallow trench isolation (STI) polish. Third, we propose a framework for the modeling of pattern dependent effects in copper CMP. The framework includes “removal rate diagrams” which concisely capture dishing height and step height dependencies in dual material polish processes.

The existence of pattern effect in films polished by CMP processes has been well documented[5][6]. Large variations in effective pattern density have been shown to result in significant and undesirablepost-polish film thickness variation. To counteract this effect, two methods are typically used to equalizethe effective pattern density across the die. The first method is a process step known as reverse etchback,where areas of high density have large portions of the raised areas etched away, ...