Chemical Mechanical Polishing (CMP) has been used in the manufacturing process for copper (Cu) damascene process. It is well known that dishing and erosion occur during CMP process, and they strongly depend on metal density and line width. The inherent thickness and topography variations become an increasing concern for today's designs running through advanced process nodes (sub 65nm). Excessive thickness and topography variations can have major impacts on chip yield and performance; as such they need to be accounted for during the design stage. In this paper, we will demonstrate an accurate physics based CMP model and its application for CMP-related hotspot detection. Model based checking capability is most useful to identify highly environment sensitive layouts that are prone to early process window limitation and hence failure. Model based checking as opposed to rule based checking can identify more accurately the weak points in a design and enable designers to provide improved layout for the areas with highest leverage for manufacturability improvement. Further, CMP modeling has the ability to provide information on interlevel effects such as copper puddling from underlying topography that cannot be captured in Design-for- Manufacturing (DfM) recommended rules. The model has been calibrated against the silicon produced with the 45nm process from Common Platform (IBMChartered- Samsung) technology. It is one of the earliest 45nm CMP models available today. We will show that the CMP-related hotspots can often occur around the spaces between analog macros and digital blocks in the SoC designs. With the help of the CMP model-based prediction, the design, the dummy fill or the placement of the blocks can be modified to improve planarity and eliminate CMP-related hotspots. The CMP model can be used to pass design recommendations to designers to improve chip yield and performance.

As part of copper (Cu) damascene manufacturing process, Chemical Mechanical Polishing (CMP) has been applied to keep the uniformity of metal thickness, and the planarity of chip/wafer to accommodate today’s shrinking lithography process window. CMP is a process that heavily depends on the metal width and density, and there is a strong interaction between design and CMP process. Dummy fills (tiling) are routinely applied to the design files to keep metal density uniform. However, due to complex natures of CMP process (pad, slurry and metal/oxide interaction, long range and multi-level effects), CMP related hotspots are often observed in the manufacturing process. CMP related issues such as Cu pooling/bridging and excessive thickness variation will have a major impact on chip yield and circuit timing and performance. Thus it is essential to correct those hotspots during circuit design stage for better yield and performance. In this paper we will introduce the use of an accurate physical based model to simulate CMP process on a full chip level and detect CMP related hotspots. We will show by using Cadence CMP Predictor (CCP), hotspots that are related to the tiling approach were detected. The CMP model can then be used to assist developing optimal tiling approach and reduce or eliminate CMP related hotspots, hence help to enhance the yield of the designs. The unique capability of detecting CMP related hotspot accurately has made CCP a valuable tool in the design flow to improve yield and performance.

Since a premetal dielectric (PMD) is used in the first level of interconnects, tight control of the critical dimension of the subsequent first-level contact is essential. The thickness nonuniformity due to PMD chemical mechanical polishing (CMP) can consume most of the depth-of-focus budget for the deep UV lithographic process, in this paper. we first describe a low pressure/high speed CMP process for PMD. Using a polishing pressure of only 2.5 psi, we improve the within die nonuniformity by 20-30%. To meet the throughput requirement, we can achieve a very high polish rate (>5000 Angstrom/min) by using high rotational speeds. Second, we describe an integrated noncontact clean to achieve low post-CMP defect counts and metallic contaminations. Cleaning phosphosilicate glass (PSG) is generally more difficult than undoped oxides. Because PSG is softer than an undoped oxide, it usually has more microscratches. Because phosphorous acts as a gettering center for metallic impurities, PSG can have high metallic contamination after post-CMP clean. HF immersion can greatly reduce the metallic contamination, but it enlarges the microscratches, leading to a large number of detectable defects. Mechanisms for the removal of slurry residue, microscratches, and metallic contamination are discussed in this paper. (C) 2000 The Electrochemical Society. S0013-4651(99)03-037-5. All rights reserved.

Chemical mechanical polishing (CMP) has become the preferred planarization method for multilevel interconnect technology due to its ability to achieve a high degree of feature level planarity. However, methods are needed to understand and model both wafer level and die level uniformity in interlevel dielectric (oxide) polishing. This paper examines the variation of die level planarity across the wafer and at different process conditions. Substantial dependency of planarization length, a characteristic length which determines die level planarity, on table speed and down pressure is found, varying from 6.2 to 7.8 mm in the experiments considered here. In addition, a dependence of planarization length on die position within the wafer is found, varying by similar to0.5 mm across the wafer resulting in a difference of similar to 300 Angstrom total indicated range from one die to the next. Some die are impacted even more strongly resulting in much smaller planarization lengths (near 5.0 mm in some cases) due to wafer edge effects. We conclude that accurate modeling and optimization of within-die variation depends on accurate modeling and measurement of not only wafer scale removal rate variation but also wafer scale planarization length variation. (C) 2000 The Electrochemical Society. S0013-4651(00)04-093-3. All rights reserved.