In this work we present a measurement approach to determine the interface trap density in FinFETs as a function of their energy. It is based on the precise determination of the gate voltage dependent ideality factor of the subthreshold current in this device. The required measurement accuracy for temperature, drain current and transconductance is derived, and we propose an implementation for wafer-level device measurement on contemporary test set-ups. Exemplary interface trap distributions are shown as obtained from two FinFET device technologies, featuring the commonly observed bathtub shape.

This paper describes the potential of tunable strain in field-effect transistors to boost performance of digital logic.Voltage-controlled strain can be imposed on a semiconductor body by the integration of a piezoelectric material improving transistor performance.In this paper, we derive the relations governing the subthreshold swing in such devices to improve the understanding.Using these relations and considering the mechanical and technological boundary conditions, we discuss possible device architectures that employ this principle.Further, we review the recently published experimental and modeling results of this device, and give analytical estimates of the power consumption.

Earlier theoretical reports predicted that the usage of a piezoelectric stressor layer around the FinFET, i.e., the PiezoFET, offers a great potential for steep subthreshold slope devices. For the first time, we analyzed the practical realization of such PiezoFETs comprising a piezoelectric stressor layer, lead-zirconate-titanate (PZT), and aluminum-nitride (AlN) deposited on n-type silicon FinFETs. A high-piezoelectric response in the range of 100 pm/V has been obtained for the PZT PiezoFET evidencing the converse piezoelectric effect in the device. The piezoelectric response for the AlN device was much less (13 pm/V) as expected. Underlying device properties, such as subthreshold swing (SS) and low-field electron mobility have been significantly affected by the presence of the PZT stressor. A 20%-50% change in the mobility and a change in the SS (about 5 mV/decade) have been observed. The change can be attributed to the strain induced reduction of the interface trap density at the Si/SiO2 interface. This strain is partly formed by the bias over the piezoelectric layer, which indicates the converse piezoelectric effect related tunable strain in both the silicon channel and gate oxide.

We realized metal-ferroelectric-metal (MFM) capacitors comprising high-quality ferroelectric lead zirconate titanate (Pb(Zr0.52Ti0.48)O-3 or PZT) thin films on an LaNiO3/poly-Si/titanium nitride (TiN)/SiO2 integrated on a 100 mm Si wafer. Promising effective piezoelectric coefficient and remnant polarization of 53 pm/V and 19.2 mu C/cm(2), respectively, are obtained for the 100 nm-PZT/20 nm-LNO stack. Further analysis of the samples indicates the presence of a passive layer, possibly near the Ti/PZT interface at the top electrode. A leakage current model has been used to explain the obtained current density electric field curves. In this model, diffusion limited transport has been assumed in which the injection is interface-controlled. Based on the capacitance and the leakage current measurements, the thickness and dielectric constant values of the passive layer are estimated to be 2.1 nm and 23, respectively. The observed apparent low barrier height value of 032 eV is attributed to ferroelectric polarization related phenomena. A good agreement between measurement and leakage current model is obtained. (C) 2014 Elsevier B.V. All rights reserved.

Metal induced strain in the channel region of silicon (Si) fin-field effect transistor (FinFET) devices has been characterized using Raman spectroscopy. The strain originates from the difference in thermal expansion coefficient of Si and titanium-nitride. The Raman map of the device region is used to determine strain in the channel after preparing the device with the focused ion beam milling. Using the Raman peak shift relative to that of relaxed Si, compressive strain values up to – 0.88% have been obtained for a 5 nm wide silicon fin. The strain is found to increase with reducing fin width though it scales less than previously reported results from holographic interferometry. In addition, finite-element method (FEM) simulations have been utilized to analyze the amount of strain generated after thermal processing. It is shown that obtained FEM simulated strain values are in good agreement with the calculated strain values obtained from Raman spectroscopy.

In this paper, we compare measurements of the conduction-band (CB) offset in [110]- and [010]-oriented narrow n-type FinFETs with a model taking into account both strain and quantum confinement. We estimate the complete strain tensor for the scarce strain measurement points available with finite-element-method simulations of the thermal expansion effect. We found an inhomogeneous compressive strain that increases for smaller fin widths. The experimental CB offset is extracted from temperature-dependent transfer characteristics. The results show a lowering of the CB edge up to 40 meV for fin widths down to 5 nm. These experimental observations compare well with the model, and hence, the band offset can be explained by both quantum confinement and strain.

Mechanisms of light emission in Tb doped Si rich SiOx matrix prepared by magnetron sputtering are studied by photoluminescence spectroscopy (PL). Characteristic PL peaks of Tb3+ ions and Si nanocrystals are simultaneously observed with an inverse relationship between their intensity. With a prolonged heat treatment at high temperatures, light emission from Tb3+ ions enhances at the expense of total quenching of the PL signal from the nanocrystals. It is suggested from the annealing studies as a function of process conditions and structural characterization that the light emission from Tb ions is mediated by trap states formed in the band gap of the oxide matrix by TbxSiyOz complexes or excess Si states.

Radiation sensors based on metal oxide semiconductor (MOS) structure are useful because of their superior sensitivity as well as excellent compatibility with the existing microelectronic technology. In this paper, a systematic study of MOS capacitors built on p- and n-type Si substrates with different SiO2 thicknesses (10nm, 50nm, 100nm and 240nm) is presented. MOS device response to gamma radiation up to 256Gray have been studied from the sensor application point of view. Variation of the radiation induced device response with oxide thickness, substrate type, applied bias and post annealing have been measured and discussed. Radiation induced charge in MOS devices is shown to be a strong function of the oxide thickness as expected. Application of a positive bias to the gate is found to enhance the device sensitivity for both n- and p-type devices. This is explained in terms of the involvement of the interface states in the sensing process. Devices have also been studied after repeated cycles of irradiation and annealing treatment under hydrogen atmosphere. Each cycle consists of gamma irradiation with 60Gray dose and an anneal at 200°C for 30min. The charging–discharging mechanism during these cycles is discussed.

In this work we investigated the properties of HSQ and PMMA resists focusing on contrast and line width for ebeam lithography (EBL) application. HSQ was found to be a good candidate to have desired line widths but the contrast we obtained was less than it was for PMMA. Since the fluorine based plasma does not have high selectivity over exposed HSQ, we propose a PMMA/HSQ bi-layer resist stack as a hard mask to etch Si selectively. Using this technique, 50nm deep Si fins may be patterned.