We demonstrate outstanding resistance-drift (R-drift) mitigation and void elimination as reliability benefits of a thin metallic liner. By tuning the resistivity of the liner, the confined PCM with a metallic liner yields an extremely low R-drift coefficient (∼0.01). We also show for the first time that confined PCM could have a self-recovering property by incorporating a metallic liner. The experimental results with real-time in-situ transmission electron microscope (TEM) exhibit the robustness of the confined PCM that can recover by itself without any extra circuits.

Doped Ga-Sb-Ge showed good thermal stability and fast switching speed. In this work, we present the results of a comprehensive reliability study for the relationship between cycling endurance and thermal stability on a 128Mb chip using modified doped Ga-Sb-Ge material. The chip exhibited good cycling endurance > 100K cycles, and there was no fail bits after soldering test. Furthermore, the chip showed no issue for 100K cycles after 260°C baking for 1000 seconds. In terms of the data retention, it was estimated that the PCM could retain data for 10 years at 215°C after 1K pre-cycles, 210°C after 10K pre-cycles, and 205°C after 100K pre-cycles. The PCM is suitable for applications requiring high thermal stability and cycling endurance.

The endurance performance of a novel confined phase change memory cell with metallic nitride liner is investigated using a transmission electron microscope (TEM). Write endurance has been shown to be substantially improved by this new structure [1]. Memory cells that had been cycled up to 109 were cross-sectioned and studied using the TEM. A majority of the electrically observed endurance failure mechanisms were stuck-SET. Physical failure analysis showed the failed cell is always associated with large void formation and material segregation. In-situ TEM analysis was used to study the void formation, accumulation and movement, where the memory cell was simultaneously operated and imaged in the TEM. Also, an interesting self-healing process of the void was recorded during the set/reset operation.

We present for the first time in-depth analysis of the outstanding endurance characteristics of an ALD-based confined phase change memory (PCM) [1] with a thin metallic liner. Experimental results confirm that both the proper metallic liner and the confined pore cell structure are required for a reliability advantage. This confined PCM with a metallic liner is found to be immune to classic endurance failure mechanisms. The void-free confined PCM yields a new record endurance (2×10 12 cycles) with stabilized elemental segregation that does not result in stuck-SET failure.

We propose and demonstrate a new low power phase change memory using a novel 3D network of crystallites with phase change confined to only at grain intersections. Contrary to conventional phase change memories, for which an entire volume of chalcogenide glass is amorphized or crystallized for high or low resistance, we propose a multi-grained structure where we only induce phase change in the inter-grain regions. This not only drastically reduces the phase change volume but also improves the thermal efficiency of the cell. 3D simulation is used to understand the local heating effect. To create the multi-grained structure we have carefully studied the Ge/Sb/Te composition, the doping material and concentration and PVD deposition conditions. Consequently, the switching current can be reduced to 20uA. Furthermore, localizing the heating also reduces thermal disturbance to neighboring cells thus provides excellent pitch scalability.

Inherent cell variation of phase change memory is difficult to control by material or device engineering alone. We previously reported R-I curve shift detection scheme as a good method for monitoring PCM cell characteristics. This paper extends that concept and proposes a Stress-trim procedure to tighten R-I characteristics for PCM MLC operation. By leveraging the right-shift phenomena of PCM R-I curves, we demonstrated that Stress-trim can effectively reduce cell variation to improve MLC performance. A MLC program current amplitude range reduction of 40% and MLC time to failure extension of nearly 150X are achieved.

A new phase change material that provides fast SET speed, high cycling endurance, and large resistance window suitable for MLC SCM is investigated. Thorough understanding of the factors that affect the resistance distribution taught us to avoid operating near the melting temperature of the phase change material. By exploiting the self-converging property of low current SET operation we have designed a novel write scheme that provides fast and accurate MLC programming. High performance and high reliability 2-bits/cell MLC is demonstrated on a 512Mb test chip.

We demonstrate a neuromorphic core with 64k-cell phase change memory (PCM) synaptic array (256 axons by 256 dendrites) with in-situ learning capability. 256 configurable on-chip neuron circuits perform leaky integrate and fire (LIF) and synaptic weight update based on spike-timing dependent plasticity (STDP). 2T-1R PCM unit cell design separates LIF and STDP learning paths, minimizing neuron circuit size. The circuit implementation of STDP learning algorithm along with 2T-1R structure enables both LIF and STDP learning to operate asynchronously and simultaneously within the array, avoiding additional complication and power consumption associated with timing schemes. We show hardware demonstration of in-situ learning with large representational capacity, enabled by large array size and analog synaptic weights of PCM cells.

Attempts to improve the retention so far must sacrifice switching speed. This work explores new phase change material based on pseudobinary GaSb-Ge system. The resulting new phase-change material has demonstrated fast switching speed of 80 ns, long endurance of 1G cycles and excellent data retention that survives 250 oC-300 hrs. The 10 years-220 oC data retention is the best ever reported. It is also the fastest material that can pass the solder bonding criteria for embedded automotive applications.

Multi-level-cell (MLC) is a critical technology to achieve low bit cost for phase change memory. However, resistance drift is an intrinsic material property that kills memory window and imposes formidable challenges for MLC. In this work, we report a radically different sensing concept that exploits the non-linear R-V characteristics of PCM that can easily accommodate 8 resistance levels in three independent 10X sensing windows (100KΩ∼1MΩ × 3) all on same read speed. Each sensing window only needs to store 2∼3 resistance levels instead of 8 levels needed in conventional MLC method, thus can tolerate resistance drift without closing the memory windows. A maximum of 16 levels of MLC is demonstrated on a 256Mb chip that is suitable for 4-bits/cell application.

We show, for the first time, a robust high aspect ratio (∼4:1) confined PCM cell which utilizes a dense and highly reliable nano-crystalline-as-deposited ALD phase change material. The 33nm diameter pore structures were filled utilizing an in-situ metal nitride liner plus nano-crystalline ALD Ge-Sb-Te material. The tuned process for depositing and integrating the phase change material brings the programming endurance to beyond 2.8×10n. We demonstrate a fast programming speed of 80ns with 10x switching and, with the aid of simulation, show a path for these elements to create a high density PCM cell suitable for Storage Class Memory.

Conventional phase change memory (PCM) stores information in amorphous/crystalline states that can be read out as HRS/LRS. In this work we report a radically different mode of storage that can concurrently and independently work with the conventional storage mode. By stressing the memory cell with current we can shift the threshold for RESET switching, and the resulting R-I curve can be used to store logic states. These two modes of storage, HRS/LRS and R-I characteristics, are completely independent and do not interfere with each other, thus allow dual-mode storage. The background (R-I mode) and foreground (HRS/LRS) data can be independently written and read. Furthermore, the total number of bits stored is the multiplication of foreground and background storage. A 4-bit per cell storage scheme is illu strated.

Traditional approaches to memory characterize the number of distinct states achievable at a given Raw Bit Error Rate (RBER). Using Phase Change Memory (PCM) as an example analog-valued memory, we demonstrate that measuring the mutual information allows optimal design of read-write circuits to increase data storage capacity by 30%. Further, we show the framework can be used for energy efficient memory design by optimizing simulations of a 1Mb memory array to consume 32% less energy/bit. This work provides an information-theoretic framework to guide the design and characterization of other analog-valued emerging memory such as RRAM and CBRAM.

A novel Cycle Alarm Point (CAP) inspection is proposed to monitor PCM cycling degradation. The degradation appears in two stages - (1) right shift of R-I during moderate cycling degradation, and (2) left shift of R-I when cycling damage is severe. We further propose an In-Situ-Self-Anneal (ISSA) procedure, such that once a CAP signal is detected, the annealing procedure is issued to rejuvenate the cells. We demonstrate, for the first time, PCM cycling degradation can be recovered repeatedly. This opens a new window to extend PCM endurance and reliability for storage class memory (SCM) applications.

We demonstrate a novel confined PCM cell structure which utilizes a metallic surfactant layer to stabilize the high (and intermediate) resistance state drift in MLC phase change memory technology. The metallic surfactant layer provides an alternative conductive path to the amorphous region during read operation, which makes the cell characteristics immune to amorphous region instabilities such as time- and temperature-dependent resistance drift and noise. The data here focuses on time-dependent drift mitigation. Analytical modeling and numerical simulations show that this cell design can achieve as much as 4× larger resistance ratio between adjacent levels in a 4-level cell. Experimental results confirm its effectiveness as a resistance drift stabilizer, showing ~6× smaller drift coefficient, resulting in a substantially reduced bit error rate.

For phase-change memory to be considered a true universal memory it would have to combine MLC storage, for low cost per bit, with adequately high endurance and at least moderate data retention. However, this appears to be particularly difficult to achieve, because of phenomena such as material segregation, which comes as an effect of cycling, and resistance drift, which is inherent in the amorphous phase and affects the stability of stored data. We present a combination of a memory cell with stable programming behavior over cycling, electrical sensing techniques and signal processing technologies, to demonstrate the viability of reliable, non-volatile, MLC storage in phase-change memory cells after extended endurance cycling.

Storage class memory (SCM) does not need long data retention (since the data are refreshed regularly) but has very stringent requirements on read/write speed and cycling endurance. Even though phase change memory (PCM) is a leading candidate currently no phase change material can satisfy both speed and endurance requirements. This is because although GST-225 is a fast switching material it suffers large volume change when melting thus limited cycling endurance. Attempts to improve the endurance so far must sacrifice switching speed. This work explores new phase change material by atomic-level engineering the doping to GST. The resulting new phase-change material has demonstrated fast switching speed of 20 ns, long endurance of 1G cycles and low reset current of 150 μA in a 128 Mb test chip. Its data retention passed 20 years-55°C criteria with failure rate lower than 10ppm.