A p-GaN gate high electron mobility transistor with the buffer avalanche triggered layer (BATL-HEMT) is experimentally demonstrated to exhibit repetitive avalanche-like behavior. One of the major limitations of conventional HEMTs is their limited avalanche capability, primarily due to the absence of an efficient removal path for the holes generated during avalanche breakdown. The local accumulation of these holes can indirectly induce severe thermal degradation, ultimately leading to potential device failure. However, in the proposed device, the unique P++P--N++ structure initiates an avalanche effect within the buffer layer, thereby activating the established hole energy dissipation pathway. Under multiple repeated breakdown testing, the device can instantaneously dissipate high current densities without observable thermal degradation. Additionally, temperature-dependent breakdown measurements show that the BATL-HEMT exhibits a positive temperature coefficient characteristic of avalanche breakdown.

In this work, the n-type resistive field plate (RFP) is proposed and experimental demonstrated on p-GaN high electron mobility transistors (RFP-HEMTs) with enhanced on-state and off-state performance simultaneously. The RFP-HEMT features a high-resistivity titanium oxynitride (TiNxOy) resistive passivation layer, which extends from the source toward the drain. Due to the surface potential (V-surf) modulation effect and the two-dimensional electron gas (2-DEG) enhancement effect, the proposed RFP-HEMTs not only realized a higher breakdown voltage (BV) in the off-state but also reduced the on-state resistance (R-ON) in the on-state. Additionally, dynamic R-ON degradation and threshold voltage (VTH) instability are effectively suppressed. Compared with the conventional insulator passivated devices, the BV of optimized RFP-HEMTs reaches 1800 V, and the figures-of-merits (FOMs) of RFP-HEMTs with the gate-to-drain distance of 20 mu m improved by 428.78% Moreover, an optimized dynamic/static R-ON ratio of 1.15 is obtained, along with a suppressed shift of VTH within 20 mV. The results demonstrate that the n-type RFP technology can improve the static and dynamic performance in p-GaN gate HEMTs.

This work demonstrates p-GaN high electron mobility transistors (HEMTs) with the resistive field plate (RFP) for simultaneously improved ON-state and OFF-state performance. The RFP-HEMT features a high-resistivity titanium oxynitride (TiNxOy) resistive passivation layer extending from the source toward the drain. Owing to the surface electric field (E-field) modulation effect and the 2-D electron gas (2-DEG) enhancement effect, the designed RFP-HEMTs not only realize higher breakdown voltage (BV) in the blocking state, but also achieve lower ON-state resistance (R-on) in the conductive state. Compared with the conventional insulator passivated devices, the optimized RFP-HEMTs with the gate-to-drain distance of 20 mu m realize the BV of 1860 V improved by 111.36%, the specific ON-state resistance (R-on,R-sp) of 5.78 +/- 0.34 m Omega & sdot;cm(2) decreased by 25.03%, and the Baliga figure of merit (BFOM) of 599 MW/cm(2) improved by 496%. Furthermore, the RFP-HEMTs exhibit an optimized dynamic/static ON-state resistance ratio, which can be attributed to the effective surface E-field modulation and the surface state filling. The results prove that the TiNxOy RFP technology offers a simple and efficacious approach to improve the device performance without the limit of BV-R-on trade-off in conventional p-GaN gate HEMT design.

In this work, the p-GaN gate HEMT with the buffer hole compensation layer (HC-HEMT) for achieving repetitive avalanche-like breakdown capability is investigated. Different from the conventional non-avalanche GaN HEMT, the HC-HEMT features a hole compensation layer in the buffer, which effectively constructs a structure for hole removal. During reverse breakdown, this hole removal structure enhances the device's ability to dissipate internal energy. The proposed device successfully possesses the ability for repetitive overvoltage, rather than experiencing irreversible thermal failure. Furthermore, the positive-temperature coefficient associated with avalanche breakdown is observed in temperature-dependence tests. To our knowledge, this is the first time that avalanche-like breakdown behavior has been observed in p-GaN gate HEMTs. The results validate that HC-HEMT is essential for enhancing the reliability of GaN HEMTs.

In this article, we experimentally propose a reverse-blocking (RB) p-GaN gate transistor with the Schottky-MIS cascode drain (CDT) for the significantly reduced forward voltage drop ( V (F) ) and ultralow reverse leakage current ( I (LEAK) ). At forward bias, electron concentration at the Schottky-MIS cascode drain is higher than that at conventional p-GaN/Ohmic drain, leading to a much lower V (F) of the Schottky-MIS CDT. When experiencing reverse bias, the Schottky-MIS cascode drain effectively protects the Schottky contact from the high reverse potential compared to Schottky drain, which is beneficial to maintain an ultralow I (LEAK) in the Schottky-MIS CDT with a p-GaN gate structure. The fabricated Schottky-MIS CDT presents a superior V (F) - I (LEAK) relationship including a greatly reduced V (F) of 3.1V as well as an ultralow I (LEAK) of 1x10 (-8) A/mm, together with a competitive reverse power figures-of-merits (FOMs) of 120MW/cm (2) . These performances suggest that the proposed Schottky-MIS CDT can be a promising candidate for low-loss RB GaN power transistors and applications requiring a better V (F) - I (LEAK) trade-off.

A novel p-GaN gate high electron mobility transistor (HEMT) with the in-situ GaN passivation (ISGP-HEMT) is experimentally proposed for the synchronously improved Baliga's Figure-of-Merit (B-FOM) and a superior dynamic on-resistance (R-ON) robustness. The ISGP-HEMT features a high-resistivity in-situ GaN passivation along the access region to linearize the surface potential, which not only realize a more uniform electric field at off-state but also enhance the two-dimensional-electron-gas (2DEG) density at on-state. Thereby the increased breakdown voltage (BV) and the reduced RON is obtained synchronously, leading to an 494% improved B-FOM compared to conventional device. Moreover, the in-situ passivation mode effectively suppresses hot-electron bombardment at the interface, substantially enhancing the robustness of dynamic RON ISGP-HEMT. These findings demonstrate that the proposed device is a highly promising candidate for low-loss GaN power applications.

In this Letter, a Ga2O3 vertical Schottky barrier diode (SBD) with self-aligned field plate and mesa termination is fabricated and studied. The combination of field plate and mesa termination can effectively make the electric field distribution uniform in the termination, and thus the proposed SBD features high breakdown voltage (BV). Moreover, to eliminate alignment deviation and simplify the fabrication process, a self-aligned etching process is developed. The experimental results show that a low specific on-resistance of 4.405 mΩ·cm2 and a high BV of 3113 V can be simultaneously derived on the proposed SBD, yielding a high power figure of merit of 2.2 GW/cm2. Meanwhile, a considerably low forward voltage of 1.53 V at 100 A/cm2 is also achieved, demonstrating the low conduction loss of the device.

Herein, AlGaN/GaN lateral diode with the Schottky-Metal-Insulator-Semiconductor (MIS) cascode anode (CALD) to optimize forward voltage drop (V-F) and reverse leakage current (I-LEAK) trade-off is proposed. In the CALD device, a normally-on Ni/HfO2/AlGaN MIS-controlled channel as well as a lateral Ni/GaN Schottky contact are cascoded at the anode. The designed normally-on MIS-controlled channel has high electron concentration at forward bias and prevents high electric-field at reverse bias, which ensure both low V-F and low I-LEAK. Meanwhile, the Ni/GaN Schottky contact with a high Schottky barrier height further suppresses the I-LEAK. As a result, the fabricated CALD demonstrates an optimized V-F-I-LEAK trade-off relationship, including a low V-F of 1.6 V and a low I-LEAK of 5.2 x 10(-8) A mm(-1) (at reverse voltage of 400 V), together with a high breakdown voltage (BV) >700 V. These high performances suggest that the CALD can be a promising candidate for GaN power diode applications requiring a better V-F-I-LEAK trade-off.

In this paper, we design and fabricate a Schottky-metal-insulator-semiconductor (MIS) cascode anode GaN lateral field-effect diode (CA-LFED) to achieve ultralow reverse leakage current (ILEAK). The device based on AlGaN/GaN high-electron-mobility-transistor (HEMT) includes a normally-off MIS-controlled channel that is cascoded with a high barrier height Schottky contact. At reverse bias, the high electric-field is effectively prevented by the normally-off MIS-controlled channel edge. Together with the high barrier height Schottky contact, this feature significantly suppresses the ILEAK. Supported by the device fabrication, the CA-LFED with high breakdown voltage (BV) > 600 V shows an ultralow ILEAK of 3.6 × 10−9 A/mm as well as a low forward voltage drop (VF) of 2.2 V. The performance suggests that the CA-LFED can be a promising candidate for ultralow ILEAK and better VF-ILEAK trade-off GaN power diode applications.

In this work, we used the Direct Laser Writing Grayscale Photolithography technology to fabricate a normally-off p-GaN gate high-electron-mobility transistor with the air-bridge source-connection. The air-bridge source-connection was formed using the Direct Laser Writing Grayscale Photolithography, and it directly connected the two adjacent sources and spanned the gate and drain of the multi-finger p-GaN gate device, which featured the advantages of stable self-support and large-span capabilities. Verified by the experiments, the fabricated air-bridge p-GaN gate devices utilizing the Direct Laser Writing Grayscale Photolithography presented an on-resistance of 36 Ω∙mm, a threshold voltage of 1.8 V, a maximum drain current of 240 mA/mm, and a breakdown voltage of 715 V. The results provide beneficial design guidance for realizing large gate-width p-GaN gate high-electron-mobility transistor devices.

In this paper, the impact of the charge compensation on the access region resistance (RACC) distributions is systematically investigated in AlGaN/GaN devices. Based-on the transmission line model (TLM) method, the RACC in AlGaN/GaN devices is extracted and compared with/without the plasma-enhanced atomic-layer-deposition (PEALD) Al2O3 passivation. The PEALD-Al2O3 could supply additional positive charges at the AlGaN surface, which serves as the effect of charge compensation. With the increased positive charge density at the passivation/AlGaN interface, the surface potential (φS) of the AlGaN barrier is significantly reduced, leading to the two-dimensional-electron-gas (2DEG) density improvement at the GaN channel layer. Supported by the device's fabrication and simulation, the charge compensation impact on the RACC is verified in both the p-GaN sample after etching and the AlGaN/GaN sample without etching. The results of this work could provide beneficial guidance to design the low on-resistance (RON) AlGaN/GaN devices.

In this paper, we demonstrate a high voltage normally-off p-GaN gate high-electron-mobility-transistor (HEMT) to realize the compatible high threshold voltage ( V TH ) and high drain current ( I D ) performance. With the optimization of the epitaxial structure, the presented device shows a significantly improved V TH . Meanwhile, by using the high-quality ALD-Al 2 O 3 passivation layer, the high I D is also realized in the device because of the access region resistance reduction. Supported by the device fabrication, the p-GaN gate HEMT delivers a V TH = 3.2 V measured by linear extrapolation, a relatively large saturation I D ( I D_SAT ) of 246 mA mm −1 , and a high breakdown voltage ( BV ) of 1830 V at 1 mA mm −1 . Among various p-GaN gate HEMTs with the I D_SAT over 200 mA mm −1 , the fabricated p-GaN gate HEMT has a competitive V TH . The results suggest that the proposed device could be a promising candidate in high V TH and I D power electronics.

In this paper, we demonstrate a high voltage normally-off p-GaN gate high-electron-mobility-transistor (HEMT) with the compatible high threshold voltage (V TH ) and high drain current (I D ) at the same time. Through exploitation of the compact and even PEALD-Al 2 O 3 passivation layer, the high I D is additionally complete within the device as a result of the reduction of the access region resistance. Meanwhile, with the optimization of the device structure, V TH is considerably improved within the actual device. Supported by the device fabrication, a comparatively large saturation I D (I D _ SAT ) of 200mA/mm, the normally-off p-GaN gate HEMT presents a V TH =4.1V measured by linear extrapolation and a high breakdown voltage (BV) of 960V. This feature recommends that the p-GaN gate HEMT in this work can be a promising candidate in high V TH and I D power devices.

An AlGaN/GaN high electron mobility transistor (HEMT) using the magnetron sputter to deposit silicon nitride (SiN) passivation layer is proposed in this paper. The AlGaN surface damage will be reduced due to the advantages of high vacuum and low temperature during the growing processes of the magnetron sputter. Therefore, compared to the conventional device adopting the passivation of the plasma-enhanced chemical vapor deposition (PECVD) SiN, the proposed HEMT shows the significantly improved on-state performance. Supported by the experiments of the PECVD/sputter-SiN dual-layer passivation, we demonstrate that the passivation/AlGaN interface quality is a key factor that affecting on-state characteristics of the devices. The results suggest that the magnetron sputter-SiN passivation is a promising candidate for AlGaN/GaN HEMT with the high on-state performance.

In this work, we demonstrate the on-chip normally-off /on AlGaN/GaN HEMTs with the compatible fabrication processes. The normally-off HEMT utilizes a p-GaN gate to deplete the 2DEG channel, while the normally-on device adopts a MIS gate without the p-GaN layer. Supported by the devices fabrication, the normally-off/on devices are realized on one chip with the same processes. A threshold voltage (V TH ) of 2.5V and a drain current (I D ) of 324mA/ mm are obtained in the normally-off p-GaN gate HEMT. And the normally-on MIS gate HEMT shows V TH =−3.3V and I D =408mA/mm. Both of the two devices present the competitive I D -V TH performances compared with the existing works. This feature suggests that the on-chip normally-off/on AlGaN/GaN HEMTs could be a promising candidate for GaN power integrated technologies.