The growing use of LiDAR systems and constrained computing resources in the automotive sector require efficient LiDAR processing. SalsaNext, a convolutional neural network for semantic segmentation, is a promising candidate for deployment in that area. To extend the research regarding its quantization and investigate its adaptability to constrained resources, a design space exploration is performed. The design space, defined by model size, topology, and compute precision, is evaluated on a Jetson AGX Orin regarding classification accuracy, latency, and energy efficiency. The results display a trade-off between classification accuracy and runtime. The smallest model evaluated in INT8 on the GPU provides the smallest latency of 14.48 ms with a mIoU score of 43.2%. A mIoU score of 47.7% at a latency of 26.92 ms can be achieved with the medium-sized model and modified topology evaluated in INT8 on the DLA. The medium-sized model with modified topology provides good classification accuracy evaluated in FP32 on the GPU with a mIoU score of 55.2% in 67.85 ms.

Synchronization of sensor devices is crucial for concurrent data acquisition. Numerous protocols have emerged for this task, and for some multi-sensor setups to operate synchronized, a conversion between deployed protocols is needed. This paper presents a bare-metal implementation of a Tri- Level Sync signal generator on a microcontroller unit (MCU) synchronized to a master clock via the IEEE 1588 Precision Time Protocol (PTP). Cameras can be synchronized by locking their frame generators to the Tri-Level Sync signal. As this synchronization depends on a stable analog signal, a careful design of the signal generation based on a PTP-managed clock is required. The limited tolerance of a camera to clock frequency adjustments for continuous operations imposes rate-limits on the PTP-controller. Simulations using a software model demonstrate the resulting controller instabilities from rate-limiting. This problem is addressed by introducing a linear prediction mode to the controller, which estimates the realizable offset change during rate-limited frequency alignment. By adjusting the frequency in a timely manner, a large overshoot of the controller can be avoided. Additionally, a cascading controller design that decouples the PTP from the clock update rate proved to be advantageous to increase the camera’s tolerable frequency change. This paper demonstrates that a MCU is a viable platform to perform PTP-synchronized Tri-Level Sync generation. Our open source implementation is available for use by the research community at https://github.com/IMS-AS-LUH/t41-tri-sync-ptp.

Modern and future AI-based automotive applications, such as autonomous driving, require the efficient real-time processing of huge amounts of data from different sensors, like camera, radar, and LiDAR. In the ZuSE-KI-AVF project, multiple university, and industry partners collaborate to develop a novel massive parallel processor architecture, based on a cus-tomized RISC-V host processor, and an efficient high-performance vertical vector coprocessor. In addition, a software development framework is also provided to efficiently program AI-based sensor processing applications. The proposed processor system was verified and evaluated on a state-of-the-art UltraScale+ FPGA board, reaching a processing performance of up to 126.9 FPS, while executing the YOLO-LITE CNN on 224x224 input images. Further optimizations of the FPGA design and the realization of the processor system on a 22nm FDSOI CMOS technology are planned.

The severe acute respiratory syndrome coronavirus 2 (SARS-CoV-2) pandemic has created a public crisis. Many medical and public institutions and businesses went into isolation in response to the pandemic. Because SARS-CoV-2 can spread irrespective of a patient's course of disease, these institutions' continued operation or reopening based on the assessment and control of virus spread can be supported by targeted population screening. For this purpose, virus testing in the form of polymerase chain reaction (PCR) analysis and antibody detection in blood can be central. Mobile SARS-CoV-2 screening facilities with a built-in biosafety level (BSL)-2 laboratory were set up to allow the testing offer to be brought close to the subject group's workplace. University staff members, their expertise, and already available equipment were used to implement and operate the screening facilities and a certified diagnostic laboratory. This operation also included specimen collection, transport, PCR and antibody analysis, and informing subjects as well as public health departments. Screening facilities were established at different locations such as educational institutions, nursing homes, and companies providing critical supply chains for health care. Less than 4 weeks after the first imposed lockdown in Germany, a first mobile testing station was established featuring a build-in laboratory with two similar stations commencing operation until June 2020. During the 15-month project period, approximately 33,000 PCR tests and close to 7000 antibody detection tests were collected and analyzed. The presented approach describes the required procedures that enabled the screening facilities and laboratories to collect and process several hundred specimens each day under difficult conditions. This report can assist others in establishing similar setups for pandemic scenarios.

Multicore processors serve as target platforms in a broad variety of applications ranging from high-performance computing to embedded mobile computing and automotive applications. But, the required parallel programming opens up a huge design space of parallelization strategies each with potential bottlenecks. Therefore, an early estimation of an application’s performance is a desirable development tool. However, out-of-order execution, superscalar instruction pipelines, as well as communication costs and (shared-) cache effects essentially influence the performance of parallel programs. While offering low modeling effort and good simulation speed, current approximate analytic models provide moderate prediction results so far. Virtual prototyping requires a time-consuming simulation, but produces better accuracy. Furthermore, even existing statistical methods often require detailed knowledge of the hardware for characterization. In this work, we present a concept called Multicore Performance Evaluation Tool (MPET) and its evaluation for a statistical approach for performance prediction based on abstract runtime parameters, which describe an application’s scalability behavior and can be extracted from profiles without user input. These scalability parameters not only include information on the interference of software demands and hardware capabilities, but indicate bottlenecks as well. Depending on the database setup, we achieve a competitive accuracy of 20% mean prediction error (11% median), which we also demonstrate in a case study.

Multicore processors serve as target platforms in a broad variety of applications ranging from high-performance computing to embedded mobile computing and automotive applications. But, the required parallel programming opens up a huge design space of parallelization strategies each with potential bottlenecks. Therefore, an early estimation of an application’s performance is a desirable development tool. However, out-of-order execution, superscalar instruction pipelines, as well as communication costs and (shared-) cache effects essentially influence the performance of parallel programs. While offering low modeling effort and good simulation speed, current approximate analytic models provide moderate prediction results so far. Virtual prototyping requires a time-consuming simulation, but produces better accuracy. Furthermore, even existing statistical methods often require detailed knowledge of the hardware for characterization. In this work, we present a concept called Multicore Performance Evaluation Tool (MPET) and its evaluation for a statistical approach for performance prediction based on abstract runtime parameters, which describe an application’s scalability behavior and can be extracted from profiles without user input. These scalability parameters not only include information on the interference of software demands and hardware capabilities, but indicate bottlenecks as well. Depending on the database setup, we achieve a competitive accuracy of 20% mean prediction error (11% median), which we also demonstrate in a case study.

This paper presents parallelization strategies for the implementation of imaging algorithms for synthetic aperture radar (SAR). Great emphasis is placed on time-domain based algorithms, namely the Global Backprojection Algorithm (GBP) and its accelerated version, the Fast Factorized Backprojection Algorithm (FFBP). Multi-core platforms are selected for implementation as some combine good performance results with moderate power consumption. The implemented algorithms support several types of parallelization, as the stages of the algorithms can be handled sequentially or interleaved. For the GBP algorithm three different data distribution schemes are investigated. For the FFBP algorithm a successive stage calculation method is compared with a combined calculation method. The performance is exemplary evaluated on the low cost/energy, yet powerful multi-core platform Odroid-XU4. All parallelization strategies show an almost linear speed-up with the number of used cores. Even though a specific multi-core platform is investigated, the design decisions are applicable for general multi-core architectures.