In this paper, we analyze how to calculate the matrix transposition in continuous flow by using a memory or group of memories. The proposed approach studies this problem for specific conditions such as square and non-square matrices, use of limited access memories and use of several memories in parallel. Contrary to previous approaches, which are based on specific cases or examples, the proposed approach derives the fundamental theory involved in the problem of matrix transposition in a continuous flow. This allows for obtaining the exact equations for the read and write addresses of the memories and other control signals in the circuits. Furthermore, the cases that involve non-square matrices, which have not been studied in detail in the literature, are analyzed in depth in this paper. Experimental results show that the proposed approach is capable of transposing matrices of 8192 × 8192 32-bit data received in series at a rate of 200 mega samples per second, which doubles the throughput of previous approaches.

This paper presents parallelization strategies for the implementation of imaging algorithms for synthetic aperture radar (SAR). Great emphasis is placed on time-domain based algorithms, namely the Global Backprojection Algorithm (GBP) and its accelerated version, the Fast Factorized Backprojection Algorithm (FFBP). Multi-core platforms are selected for implementation as some combine good performance results with moderate power consumption. The implemented algorithms support several types of parallelization, as the stages of the algorithms can be handled sequentially or interleaved. For the GBP algorithm three different data distribution schemes are investigated. For the FFBP algorithm a successive stage calculation method is compared with a combined calculation method. The performance is exemplary evaluated on the low cost/energy, yet powerful multi-core platform Odroid-XU4. All parallelization strategies show an almost linear speed-up with the number of used cores. Even though a specific multi-core platform is investigated, the design decisions are applicable for general multi-core architectures.

The question if new embedded low power Graphic Processing Units (GPUs) can compete with Field Programmable Gate Arrays (FPGAs) in terms of performance and efficiency is addressed. A Virtex 6 and a Virtex Ultrascale+ FPGA are compared to a Jetson TX2 GPU. Instead of basing the comparison on manufacturer reference numbers, hand optimized high performance implementations of the Fast Factorized Backprojection (FFBP) algorithm for Synthetic Aperture Radar (SAR) image generation have been investigated. Performance is measured in image lines per second and efficiency in performance per power. The Virtex Ultrascale+ provides a runtime speed-up of about 6.5x and an efficiency improvement of about 4.3x compared to the Jetson TX2 GPU.

This paper introduces a new FPGA architecture optimized for Frequency Modulated Continuous Wave (FMCW) Synthetic Aperture Radar (SAR). The architecture implements a Global-Backprojection-Algorithm (GBP) which has been modified to be independent of platform velocity (start-stop-approximation). The design supports parallelism of dedicated GBP processing modules in order to provide high performance. Compared to a MATLAB implementation on a single core Intel i5 at 3.2 GHz the dedicated implementation on a ML605 board provides a minimum speed-up factor of 94. The entire FPGA system was tested with real-life SAR data.

This paper presents a rail-based near-field FMCW-SAR system, used for generating data with up to 25.6 GHz bandwidth at velocities up to 4 m/s. System parameters like squint or depression angel are freely adjustable. Image processing is implemented on an FPGA-based hardware in real-time with the backprojection algorithm. Results are optically projected onto the scene for verification. As a practical example, the consequence of a start-stop-approximation violation with varying velocity and ramp-length is shown. Additionally, the correction of this violation is investigated.

This paper introduces a resource-scalable FPGA architecture for backprojection-based stripmap SAR imaging. Low energy consumption and small system dimensions allow for both, ground-based and airborne SAR applications. The architecture is independent from a specific FPGA-based evaluation platform, as it is integrated on a single FPGA and requires only common external memory periphery. The degree of independence is increased further by encapsulating the developed architecture or BackProjection Module (BPM) in a framework that handles external periphery addressing. This allows the user to switch evaluation platforms without the need to adapt the BPM. Scalability is provided by the option for parallelization of the BPM, thereby any FPGA can be exhausted in terms of resource utilization. This way the trade-off between throughput capacities and resource-effort can be adjusted to choose an application suitable platform. The entire system was tested on a variety of emulation platforms at different parallelization levels.

This paper presents the potential of standard frequency domain based SAR image generation techniques for real-time short-range FMCW applications. Exemplarily, a Range-Doppler algorithm is implemented in hardware and evaluated for a 80 GHz, 25 GHz bandwidth FMCW system. For implementation a hardware-in-the-loop framework is presented, capable of coupling high-level MATLAB code with different hardware evaluation environments. This allows for a gradual swap of time-critical signal processing tasks from software to hardware. The stepwise swap makes a precise analysis of discrete algorithmic stages possible, leading to an optimized hardware description. A dramatic increase of computation speed can be observed compared to time domain based image generation techniques.

The data throughput of SDRAMs is significantly reduced by the control overhead required for access or transposition of large two-dimensional data matrices stored in SDRAM memories. In this paper, a new address mapping scheme is introduced, taking advantage of multiple banks and burst capabilities of modern SDRAMs. In this way, the data throughput is maximized when reading or writing rows or columns of a two-dimensional data matrix. Other address mapping strategies minimize the total number of SDRAM page-opens while traversing the two-dimensional index-space in row or column direction. In order to achieve a higher data throughput, the new approach uses an alternative bank interleaving method to hide additional wait cycles. In this way, the number of data bus wait cycles do not depend on the overall number of page-opens directly any more. It is shown, that the data bus utilization can be increased significantly. In particular, the new mapping strategy is optimized for access of parallel samples, distributed among a number of SDRAM chips. Therefore, double buffering can be omitted. As a special operation, 2D-FFT processing for radar applications is considered. Depending on SDRAM parameters and dimensions, a continuous bandwidth utilization of 96–98 % is achieved for accesses in both matrix dimensions, including all page-opens and refresh operations.

In this paper, an FPGA based hardware architecture for airborne real-time SAR image generation with integrated first-order motion compensation (MoCom) is presented. By sharing the same FPGA resources for image generation and correction of highly squinted flight path deviations, only marginal overhead in terms of additional hardware resources is required when compared to an implementation without resource sharing. The proposed architecture has been implemented and evaluated on a Xilinx Virtex-6 ML-605 Evaluation Kit for different flight path deviation and squint parameter settings. An average throughput rate of 25 MSamples/s (32-bit/sample) is reached while the FPGA resource allocation does not exceed 50% of the LUT slices (logic), 45% of the BRAM36 (memory) and less than 8% of the DSP48 slices.

Abstract. The stereo matching method semi-global matching (SGM) relies on consistency constraints during the cost aggregation which are enforced by so-called penalty terms. This paper proposes new and evaluates four penalty functions for SGM. Due to mutual dependencies, two types of matching cost calculation, census and rank transform, are considered. Performance is measured using original and degenerated images exhibiting radiometric changes and noise from the Middlebury benchmark. The two best performing penalty functions are inversely proportional and negatively linear to the intensity gradient and perform equally with 6.05% and 5.91% average error, respectively. The experiments also show that adaptive penalty terms are mandatory when dealing with difficult imaging conditions. Consequently, for highest algorithmic performance in real-world systems, selection of a suitable penalty function and thorough parametrization with respect to the expected image quality is essential.

The development of efficient hardware architectures for real-time SAR applications demands for an intense analysis of image formation algorithms. Especially the conversion to alternative number representations in terms of efficient hardware ressource allocation is a crucial task. For the error-sensitive Wavenumber Domain Algorithm (ω-k), minimum accuracy boundaries are evaluated. Therefore, this paper introduces an integrated simulation and verification framework which covers the entire development cycle up to the dedicated data path configuration in fixed-point arithmetic. This conversion significantly contributes to an efficent ressource allocation and reduced hardware costs.

This paper presents the design of a compact real-time SAR hardware architecture for small unmanned aerial vehicles (UAVs). The architecture is flexible for a variety of SAR algorithms whereby the focus of this paper is on the wavenumber domain (ω-k) algorithm. Characteristics of the RISC/FPGA based hardware architecture are real-time processing for sensor data rates of 300 Mbit/s with image dimensions of 8k × 4k pixel, implemented on a 233 × 160 mm printed circuit board with a total power dissipation below 15 W.

When transposing large matrices using SDRAM memories, typically a control overhead significantly reduces the data throughput. In this paper, a new address mapping scheme is introduced, taking advantage of multiple banks and burst capabilities of modern SDRAMs. Other address mapping strategies minimize the total number of SDRAM page-opens while traversing the two-dimensional index-space in row or column direction. The new approach uses bank interleaving methods to hide wait cycles, caused by page-opens. In this way, data bus wait cycles do not depend on the overall number of page-opens directly. It is shown, that the data bus utilization can be increased significantly, in particular, if memories are accessed with parallel samples. Therefore, double buffering can be omitted. As a special operation, 2D-FFT processing for radar applications is considered. Depending on SDRAM parameters and dimensions, a continuous bandwidth utilization of 96 to 98% is achieved for accesses in both matrix directions, including all refresh commands.

A new FFT architecture for real-time implementation of large FFTs is presented. The architecture supports both, high-throughput and variable-length processing capabilities. The implementation is configurable at run-time, in order to compute power-of-two length ranging from 16 to 2n. It supports efficient integration of data scaling techniques. A radix-23 DIT FFT algorithm is derived, which minimizes the number of multipliers and supports simple reordering.

This paper presents the design, implementation and evaluation of new parallelization schemes for performing dense disparity estimation based on non-parametric rank transform and semi-global matching on Graphics Processing Units (GPUs). A detailed analysis of the performance limitating factors (memory throughput, instruction throughput, etc.) for each part of the parallel implementation is performed. Thus, a highly optimized mapping for each parallelization scheme onto the resources of the GPU is obtained. The resulting implementation performs disparity estimation at 27 frames per second for 1024×768 pixel images with 128 disparity levels on a Nvidia Tesla C2050 GPU.

A compact RISC/FPGA based hardware architecture for high resolution SAR signal processing is presented. Sensor data rates above 300 Mbit/s and image dimensions of 8k × 4k pixels are processed in real-time. A maximum power consumption of less than 16 W enables for usage on small UAVs.

This paper presents the mapping of an object detection application for aerial image based vehicle detection on highways onto a configurable heterogeneous RISC/coprocessor architecture. An extended pipelined processing scheme exploits the coprocessor features for parallel task processing. An alternative latency minimized processing scheme removes data dependencies in the application and improves parallel task processing capabilities. The coprocessor is mapped onto a Xilinx Virtex-5 FPGA of a RISC/FPGA-based embedded system board. The RISC in combination with the configurable coprocessor, running at 100 MHz, is capable of processing either up to 28.7 Full HD frames per second or reducing of system latencies to less than 55 ms. Therefore, this approach can be used to map complex object detection applications with high demands on throughput and latency onto the architecture.

Dieser Beitrag behandelt die Abbildung eines videobasierten Verfahrens zur echtzeitfähigen Auswertung von Winkelhistogrammen auf eine modulare Coprozessor-Architektur. Die Architektur besteht aus mehreren dedizierten Recheneinheiten zur parallelen Verarbeitung rechenintensiver Bildverarbeitungsverfahren und ist mit einem RISC-Prozessor verbunden. Eine konfigurierbare Architekturerweiterung um eine Recheneinheit zur Auswertung von Winkelhistogrammen von Objekten ermöglicht in Verbindung mit dem RISC eine echtzeitfähige Klassifikation. Je nach Konfiguration sind für die Architekturerweiterung auf einem Xilinx Virtex-5-FPGA zwischen 3300 und 12 000 Lookup-Tables erforderlich. Bei einer Taktfrequenz von 100 MHz können unabhängig von der Bildauflösung pro Einzelbild in einem 25-Hz-Videodatenstrom bis zu 100 Objekte der Größe 256×256 Pixel analysiert werden. This paper presents the mapping of a video-based approach for real-time evaluation of angular histograms on a modular coprocessor architecture. The architecture comprises several dedicated processing elements for parallel processing of computation-intensive image processing tasks and is coupled with a RISC processor. A configurable architecture extension, especially a processing element for evaluating angular histograms of objects in conjunction with a RISC processor, provides a real-time classification. Depending on the configuration of the architecture extension, 3 300 to 12 000 look-up tables are required for a Xilinx Virtex-5 FPGA implementation. Running at a clock frequency of 100 MHz and independently of the image resolution per frame, 100 objects of size 256×256 pixels are analyzed in a 25 Hz video stream by the architecture.