Abstract Projected phase-change memory (PCM) devices have been proposed as a solution to the challenge of resistance drift, an issue where PCM cell resistance increases as a function of time. Here, we theoretically and experimentally study the performance of projected mushroom PCM cells. Using circuit models, we show that the effective drift coefficient of projected PCM cells is proportional to the fraction of the current flowing through the drifting material. To further characterize device operation, we utilize a finite element model and find that tuning the projection liner sheet resistance enables a dynamic range, the ratio of the RESET resistance to the SET resistance, of 14 with a thin 2-nm projection liner. Additionally, we show that increasing the doping level provides a useful tuning knob to increase SET and RESET resistance without sacrificing dynamic range or drift performance. We fabricate projected PCM mushroom cells on 300-mm wafers to calibrate the model parameters and find that experimental trends are consistent with these theoretical predictions. Impact statement Resistance drift presents a significant challenge in leveraging phase-change memory (PCM) for neuromorphic computing applications. Projected PCM devices offer an alternative design to significantly reduce resistance drift by bypassing the high-drift amorphous PCM material with a lower resistance parallel resistor during the read operation. Although projected PCM bridge cells have been successfully demonstrated, they can be challenging to fabricate reliably on a wafer scale due to inherent etch damage and variability near the active region. Here, we study the performance of the projected PCM mushroom cell, a design that offers a more manufacturable route to fabricate the large arrays of cells needed for analog artificial intelligence hardware. Using finite element method simulations and equivalent circuit models, we highlight the tradeoff between minimizing drift and achieving large dynamic range when increasing the liner sheet resistance. We show that thinner liners enable the largest dynamic range and that the PCM doping can be used to tune the cell SET and RESET resistances. Using this insight, we fabricate projected PCM mushroom cells on 300-mm wafers at the IBM Research AI Hardware Center and confirm these theoretical predictions. Our work, therefore, demonstrates the manufacturability of projected PCM cells for analog computing. Graphical abstract

As the semiconductor industry turns to alternate conductors to replace Cu for future interconnect nodes, much attention as been focused on evaluating the electrical performance of Ru. The typical hexagonal close-packed (hcp) phase has been extensively studied, but relatively little attention has been paid to the face-centered cubic (fcc) phase, which has been shown to nucleate in confined structures and may be present in tight-pitch interconnects. Using \emph{ab initio} techniques, we benchmark the performance of fcc Ru. We find that the phonon-limited bulk resistivity of the fcc Ru is less than half of that of hcp Ru, a feature we trace back to the stronger electron-phonon coupling elements that are geometrically inherited from the modified Fermi surface shape of the fcc crystal. Despite this benefit of the fcc phase, high grain boundary scattering results in increased resistivity compared to Cu-based interconnects with similar average grain size. We find, however, that the line resistance of fcc Ru is lower than that of Cu below 21 nm line width due to the conductor volume lost to adhesion and wetting liners. In addition to studying bulk transport properties, we evaluate the performance of adhesion liners for fcc Ru. We find that it is energetically more favorable for fcc Ru to bind directly to silicon dioxide than through conventional adhesion liners such as TaN and TiN. In the case that a thin liner is necessary for the Ru deposition technique, we find that the vertical resistance penalty of a liner for fcc Ru can be up to eight times lower than that calculated for conventional liners used for Cu interconnects. Our calculations, therefore, suggest that the formation of the fcc phase of Ru may be a beneficial for advanced, low-resistance interconnects.

We study grain boundary scattering as a source of resistance increase in narrow interconnects. We consider both copper and a potential next-generation metal, ruthenium. The increase in resistance due to grain boundary scattering is often calculated using the Mayadas and Schatzkes model, which in addition to the average grain size depends on the bulk resistivity, the electron mean free path, and the average reflection coefficient at grain boundaries. We demonstrate a workflow to calculate all the latter three material properties using first-principles calculations. Calculated values for copper are used to verify our method, while experimental results for the cubic phase of ruthenium are unavailable and thus must rely on first-principles calculations. Using an automated workflow, we consider significantly more grain boundary structures than in other works, and find an almost twice as large average reflection coefficient for copper than previously reported. In spite of the larger copper reflection coefficient, the corresponding reflection coefficients for ruthenium grain boundaries are consistently larger, but with a smaller variation than observed for copper. Our results demonstrate the importance of studying a large set of grain boundary structures.

We use first-principles calculations to investigate the structural and transport properties of various Cu/Ta(N)/Cu interface stacks, which are representative of the metal interfaces located at the bottom of vertical interconnects in state-of-the-art back-end-of-line technology. In particular, we consider approximately 2-nm thick layers of several different Ta-based barrier layers sandwiched between two Cu(111) layers, including TaN, α-Ta, β-Ta, and a bilayer TaN/α-Ta structure. Our results highlight that the bilayer Cu/TaN/α-Ta/Cu structure shows both an attractive combination of low electrical resistance and superior dielectric adhesion. We also find that inelastic phonon transport across the interface structures is largely determined by the frequency overlap of the bulk-like phonon density of states of each metal layer. Our results are fed into a simple interconnect performance benchmarking model based on a single-driver signal wire, where we find that metal barrier optimization can result in a net 2.5% stage delay reduction without comprising reliability.

We present a combined experimental and theoretical study of via resistance modulation in Cu interconnects with ultra-scaled diffusion barriers and wetting layers. In particular, we demonstrate that reducing the thickness of the TaN-based diffusion barrier below 1 nm results in a decrease in the measured via resistance, while reducing the thickness of the Co wetting layer below 1 nm has virtually no impact on via resistance. These results are explained using first-principles transport calculations, which show that a 1 nm thick TaN layer is more effective in blocking electrons than a 1 nm thick Co layer. Measurements of time-dependent dielectric breakdown indicate that scaling either TaN or Co layers below 1 nm in thickness results in degraded reliability. These results suggest that there is minimal value in scaling the thickness of Co wetting layers below 1 nm, while scaling TaN diffusion barriers below 1 nm results in a trade-off between performance and reliability.

The vertical resistance of Cu/Ta/Ru/Cu stacks is calculated using a combination of first-principles density functional theory (DFT) and a Non-Equilibrium Green's Function (NEGF) formalism. The effects of oxidizing either one or both of the Ta and Ru layers are analyzed. These oxides can be either metallic (TaO and RuO2) or insulating (Ta2O5) in nature. Simulations indicate that for the metallic oxides, the presence of RuO2 results in more electron scattering than TaO. Complete oxidation of both Ta/Ru layers results in a ≈3× increase in resistance for Cu/TaO/RuO2/Cu relative to the un-oxidized structure, and a ≈8x increase in resistance for Cu/Ta2O5/RuO2/Cu relative to the un-oxidized structure. Electron transmission/reflection coefficients as well as values of total resistance are reported for each interface structure. These results highlight the importance of identifying and controlling oxygen contamination in high-volume manufacturing in order to obtain low resistance vertical interconnects and favorable device performance.

We demonstrate a simulation workflow based on first-principles calculations to rapidly screen candidate materials for viability as ferromagnetic electrodes in magnetic tunnel junctions (MTJs) for the next generation of high-performance magnetic random access memory (MRAM) technology. For a series of Fe-based alloys with a fixed crystal structure, we calculate formation energies, bulk spin polarization, and essential magnetic properties including magnetic anisotropy energy (MAE) and tunneling magnetoresistance (TMR). This work demonstrates a materials optimization strategy that can guide on-wafer experiments.

In this paper, we present for the first time a “Gate-Cut-Last” integration scheme completed within the Replacement Metal Gate (RMG) module. This novel gate cut (CT) technique allows the scaling of gate extension length past the end fin which reduces parasitic capacitance, leakage and performance variation. In addition, we demonstrate that CT-in-RMG is a promising alternative integration process that can enable scaling for future logic technology nodes. Device, circuit and reliability results are shown to compare this novel CT-in-RMG process to the conventional gate cut method.

We use state-of-the-art ab initio simulation methods to study fundamental electron scattering mechanisms in cobalt conductors for applications in advanced interconnect technology. In particular, we consider electron scattering at intrinsic defect sites, twin grain boundaries, and at the Co/metal/Co interfaces present in vertical interconnects. Effective resistivity values and reflection coefficients are calculated in each case. The explicit treatment of electron spin results in distinct majority and minority spin behavior, with majority spin states exhibiting less scattering than minority states. Our results indicate that grain boundary scattering dominates over scattering at intrinsic point defect sites. Vertical resistance calculations indicate that Co vias can have substantially lower resistance than corresponding Cu vias at comparable dimensions. These results help build a fundamental understanding of electron scattering mechanisms in non-Cu conductors for advanced interconnect applications.

Low Ge content SiGe-based CMOS FinFET is one of the promising technologies [1-2] offering solutions for both high performance and low power applications. In this paper, we established a competitive SiGe-based CMOS FinFET baseline and examined various elements for high performance offering. The performance elements in gate stack, channel doping, contact resistance, and junction have been explored to provide a cumulative 20% / 25% (n/pFET) performance enhancement. These elements provide a viable path towards performance enhancement for future technology nodes.

A hybrid approach to model the effect of random dopant fluctuations in low doped FinFETs is proposed. Existing Monte Carlo and atomistic approaches are found to be inadequate to capture device variability correctly when applied independently. Instead a hybrid methodology which uses an atomistic approach in low doped regions and Monte Carlo everywhere else is developed. The hybrid approach is shown to capture the threshold voltage variability adequately. Comparison with analytical results for planar MOSFETs shows an excellent agreement and establishes the validity of the approach. The results suggest that accurate modeling of low doped regions is essential to be able to estimate variability correctly.

We present a fully integrated 14nm CMOS technology featuring finFET architecture on an SOI substrate for a diverse set of SoC applications including HP server microprocessors and LP ASICs. This SOI finFET architecture is integrated with a 4th generation deep trench embedded DRAM to provide an ultra-dense (0.0174um2) memory solution for industry leading `scale-out' processor design. A broad range of Vts is enabled on chip through a unique dual workfunction process applied to both NFETs and PFETs. This enables simultaneous optimization of both lowVt (HP) and HiVt (LP) devices without reliance on problematic approaches like heavy doping or Lgate modulation to create Vt differentiation. The SOI finFET's excellent subthreshold behavior allows gate length scaling to the sub 20nm regime and superior low Vdd operation. This leads to a substantial (>35%) performance gain for Vdd ~0.8V compared to the HP 22nm planar predecessor technology. At the same time, the exceptional FE/BE reliability enables high Vdd (>1.1V) operation essential to the high single thread performance for processors intended for `scale-up' enterprise systems. A hierarchical BEOL with 15 levels of copper interconnect delivers both high performance wire-ability as well as effective power supply and clock distribution for very large >600mm2 SoCs.