Atomic-scale observations by STM and TEM of the early stages of film growth and recent studies of the detailed composition of beams from ICB sources have led to new understandings of origins of some of the extraordinary properties of thin films deposited by ICB methods. The presence of a small fraction of atoms in the form of large clusters initiates a novel sequence of film growth steps starting with the immediate formation of stable islands for film growth. The growth of films from cluster-initiated islands leads to fundamentally altered film properties (compared to atomic beam, MBE, deposition) such as the epitaxial alignment of metal/semiconductor/ceramic multilayers grown near room temperature.

Epitaxial Al films have been grown on heavily doped Si(100) by neutral cluster beam deposition. The Al films were evaluated by RBS, RHEED, optical interference roughness maps and STM imaging. The results were consistent with the formation of epitaxial Al (110) bi-crystals similar to films grown by ionized cluster beam deposition on lightly-doped Si.

Preliminary studies of radiation damage and recovery of E 2 PROM sensor devices following exposure to a high-dose, 1 MeV proton beam give encouragement to the use of H-cut and layer transfer methods for vertical integration of 3D-IC's with fully-formed CMOS devices and metal interconnect.

A novel silicide process with two-step low temperature microwave annealing (MWA) achieves NiSi thickness of 10 nm while maintaining low resistance, and an ultra-thin Ni silicide film, only 4.5 nm, has been realized. In this MWA system, we insert quartz and Si susceptors to change the absorption efficiency of the process wafer and provide fine turning in temperature control during annealing. The thickness of NiSi film is determined by microwave power and by changing the number and the position of quartz and Si susceptors in the first step of the anneal process. The STEM-HAADF combined EELS/EDS spectroscopies are used to analyze the electronic excitations and identify the phase of Ni silicide. (C) 2014 The Electrochemical Society. [DOI: 10.1149/2.006405jss] All rights reserved.

For the first time, a novel junctionless (JL) FinFET structure with a shell doping profile (SDP) formed by molecular monolayer doping (MLD) method and microwave annealing (MWA) at low temperature is proposed and studied. Thanks to the ultra thin SDP leading to an easily-depleted channel, the proposed JLFinFET can retain the ideal subthreshold swing (~ 60 mV/dec) at a high doping level according to simulations. Poly Si based JLFinFETs processed with MLD and MWA exhibit superior subthreshold swing (S.S. ~ 67mV/dec) and excellent on-off ratio (>10 6 ) for both n and p channel devices. Threshold voltage (V TH ) variation due to random dopant fluctuation (RDF) is reduced in MLD-JLFinFETs, which can be attributed to the molecule self-limiting property of MLD on the Si surface and quasi-diffusionless MWA at low temperature. Our results reveal the potential of the proposed SDP enabling a JLFET showing reduced variation and outstanding performance for low power applications.

1 National Nano Device Laboratories, Hsinchu, Taiwan; 2 Department of Electronics Engineering, National Chiao Tung University, Hsinchu, Taiwan; 3 Department of Electronics Engineering, I-Shou University, Kaohsiung, Taiwan; 4 Department of Electronics Engineering, Chung Hua University, Hsinchu, Taiwan; 5 Current Scientific, San Jose, CA, USA; 6 Department of Physics, National Chung Hsing University, Taichung, Taiwan. Tel: +886-3-5726100-7793, Fax: +886-3-5722715, *Email: yjlee@ndl.narl.org.tw Abstract Ge MOSFETs with all thermal processes preformed by microwave anneal (MWA) has been realized. The full MWA process is <390 C. It significantly outperforms conventional RTA process in 3 aspects: (1) diffusion-less junction, (2) increased Cox and healed gate dielectric/channel interface, and (3) ultrathin 7.5nm nickel mono-germanide with lower sheet resistivity and contact resistivity. Compared to conventional RTA, the MWA gives 50% and 24% drive current enhancement for pand n-MOSFET, respectively. These data show that the low temperature MWA is a promising thermal process technology for Ge MOSFETs manufacturing. Introduction For dopant activation in Ge MOSFETs, RTA process >600 o C have been wildly adopted[1-2]. Such high temperature process causes the degradation of gate dielectric/ Ge channel interface, and results in severe dopant diffusion in source/drain region with Ge out-diffusion. In addition, for lowering the contact resistance to germanium, NiGe is the most promising candidate due to its low resistivity [3-4]. In order to thin down the thickness of NiGe, reducing the process temperature is necessary. However, a lower temperature results in a higher silicide resistance due to the small crystallite size. MWA is promising for achieving advanced Ge MOSFETs because of its unique low temperature due to apparent non-thermal energy transfer that is not yet fully understood[5]. The advantages for Ge MOSFETs with MWA are summarized in Fig. 1. Results and Discussion Diffusion-Less Junction. The n + and p + doping are introduced by P and BF2 implants at a dose of 1×10 15 cm -2 , respectively. The peak temperature of dopant activation by MWA was 390 o C. Fig. 2(a) shows a significant diffusion of P after RTA and no P diffusion after MWA. For boron, comparable diffusion-less concentration profiles after MWA and RTA are observed and presented in Fig. 2(b). The activated levels of P and B after MWA are 2×10 19 cm -3 and 7.5×10 19 cm -3 , respectively. In Fig. 4, the deep junction of P formed by RTA results in the lower Rs. Thus, ultra shallow junctions can clearly be reached by the low temperature MWA. Gate Dielectric/Channel Interface. The TiN/Al2O3/GeO2 structure of the nand p-MOS capacitors for C-V characterizations were fabricated on (100) bulk Ge. After interfacial layer formation, Al2O3 was deposited by ALD. From Figs. 4 and 5, an increase of Cox and a decrease of the interfacial trap density after MWA were observed. The gate capacitance increases after MWA, which is due to less Ge out-diffusion during low temperature MWA than RTA. The device on/off characteristics are in Figs. 6 and 7. Compared to RTA, MWA produces 50% and 24% drive current enhancements for pand n-MOSFET, respectively. Their off leakage currents are similar to those by RTA processing. Ultrathin 7.5nm Ni Mono-Germanide. In Fig. 8(a), a 7.5 nm NiGe is produced by MWA which meets the target of year 2022 in the ITRS roadmap[6]. The NiGe layer is fabricated on (100) epi-Ge on Si. Unreacted metal was removed after the 1 st anneal. Afterward, the 2 nd anneal was performed. The TEM images show an ultrathin NiGe layer with a smooth interface fabricated by MWA at two different microwave power levels during the 2 nd anneal. Fig. 8(c) shows the result of RTA germanide anneal. The NiGe thickness by RTA is about 2 nm thicker than by MWA. The temperature ramp up curves of MWA for NiGe formation are shown in Fig. 9. The temperature ramped at 2 to 6 o C/sec depending on the microwave power. In Fig. 10, Rs of NiGe by two-step MWA or RTA are summarized. Lower Rs could be obtained by increasing the MWA power with shortened process time, which lowers the peak temperature by 40 o C compared to RTA. In Fig. 11(a), the XRD spectrum for the anneal condition of MWA 145 o C + MWA 270 o C shows strong (111) preferred crystal orientation. In Fig 11(b), an increasing power with shortened process time of 2 nd step annealing leads to a larger crystallite size. In addition, by lowering the 1 st step annealing temperature of RTA for reducing the thickness of NiGe, a low intensity of RTA 150 o C + RTA 330 o C shows that it is hard to achieve both the well-defined crystalline structure and the scaling of the NiGe layer. However, the MWA results show that a thinner and lower Rs of NiGe layer was obtained because of the increased crystallinity at low temperature. Conclusion For the first time, Ge MOSFETs with all thermal processes performed by microwave has been realized. Diffusion-less junctions were achieved in Ge was induced by MWA. Compared to the conventional RTA, all MWA processing yields 24% and 50% drive current enhancements for nand p-MOSFET, respectively due to increased of Cox and better gate dielectric/Ge interface. Finally, a record ultrathin 7.5 nm nickel mono-germanide thickness is achieved by two-step low temperature MWA process. References: [1] G.-L. Luo et al., IEDM Tech. Dig., p. 689, 2009. [2] J. H. Park et al., IEDM Tech. Dig., p. 389, 2008. [3] S. Y. Lim et al., Appl. Phys. Lett. 97, 182104, 2010. [4] K. Martens et al., IEDM Tech. Dig., p.429, 2010. [5] J. H. Booske et al., J. Mater. Res., Vol. 7, p. 495, 1991. [6] ITRS Roadmap 2011. Extended Abstracts of the 2013 International Conference on Solid State Devices and Materials, Fukuoka, 2013,

Effects of microwave (MWA) at ≈500 C and rapid-thermal annealing at 600 to 1000 C are compared for phosphorous-doped, strained Si(100) and (110) implanted with molecular Carbon (C7H7) ions. Substitutional Carbon levels at 1.44% were achieved for P-doped, C7 implanted strained nMOS S/D type junctions with MWA.

Mass overlaps occurring as a result of extraction of ions from an arc discharge and gas collisions, producing molecular break up and charge exchange in the accelerator beamline, are examined for ion implantation into compound semiconductors. The effects of the choice of plasma gas elements for Be+ implants are examined as an example.

For the first time, Ge CMOS with all thermal processes performed by microwave annealing (MWA) has been realized. The full MWA process is under 390 o C. It significantly outperforms conventional rapid thermal annealing (RTA) process in 3 aspects: (1) Diffusion-less junction: for easily diffused n-type dopant, phosphorous (P), the ion implantation dopant profile after the MWA activation process remains unchanged. (2) Increased C ox and lower gate leakage: the low temperature activation process leads to less Ge out-diffusion during MWA than RTA, suppressing the degradation of gate dielectric/ Ge channel interface. (3) Ultrathin 7.5nm Ni mono-germanide with low sheet resistance (Rs) and contact resistivity: after two-step MWA, a thin mono-NiGe layer was obtained which has larger crystallite size to lower Rs. Ge n- and p-MOSFET were also demonstrated. Compared to conventional RTA, the MWA gives 50% and 24% drive current enhancement for p- and n-MOSFET, respectively. These data show that the low temperature MWA is a very promising thermal process technology for Ge CMOS manufacturing.

Photoreflectance (PR), using a uv (374 nm) diode laser probe beam, and Raman spectroscopy, using a multi-wavelength Ar+ laser coupled to a high-resolution multi-wavelength spectrometer, were used to characterize the strain relaxation of Si top layers grown on a graded and relaxed SiGe buffer stack with a final Ge concentration of 20%. The Si top layer thicknesses ranged from 1.6 to 18 nm. Considerable radial variation in the strain relaxation was seen in all sampled wafers, highlighting the need for rapid, local strain characterization. Strong correlation between shift in the Si layer dielectric response, measured by uv-PR, and the Si top layer strain, measured by Raman, is reported.

Contamination of implanted surfaces by metals and dopants is a significant limitation to the use of high-dose implantation for semiconductor IC fabrication. RBS, SIMS, SRP, chemical etching and IC device parameter measurements have been used to characterize contaminated surfaces implanted with modern, production-type implanters. Levels of dopant cross-contamination of the order of 10% of the primary dose have been observed. A systematic study of the effects of As, P, B and Sb implanted Si has shown measurable effects on diffusion profiles and junction depths at contamination levels as low as 0.01% of the primary dose. These effects are particularly serious for fast-diffusing contaminants in slow-diffusing primary dopants (such as P contamination in As implants). Evidence has been found for both sputtering and ‘vaporization’ mechanisms for transfer of contaminants from implanter surfaces to the wafer target. The effectiveness of machine design choices and process procedures (such as wafer clamp design, post-implant chemical cleans, and the use of screen oxides) in minimizing the effects of contamination are discussed.

As the drive towards the production of 100 nm CMOS devices pick up speed, the practical aspect of transistor shallow junction formation, including a large menu of process integration issues, must now be solved in a short order. The most direct path to 50 nm junction depths is through the sub-keV boron implantation and rapid thermal annealing. The material aspects of the process integration centers on: (1) CMOS devices for shallow, highly-activated and abrupt junctions (involving the choice of ion species [B, BF, B10H14, BSi2, etc.], substrate materials [ Cz, Epi, SOI], anneal conditions [ramp rate, soak time, ambient gas], etc.) and (2) Defect-dopant interactions during annealing (including surface reactions of high concentration species [B, F], diffusion and carrier trapping by background and co-implanted species [C, 0, F, etc.]. Process data for atomic and electrical activity profiles as well as defect and interface structures will be presented to illustrate progress towards understanding these complex process interactions. A particular focus will be the effects of anneal ambient and rapid temperature rise times approaching the “pike” anneal ideal.

In this paper we present results for amorphous layer thickness and interface roughness for various cluster carbon ions as well as monomer carbon implants for various doses implanted at different implant temperatures. The effect of cluster size, implant dose, implant dose rate and wafer implant temperatures are discussed based on Spectroscopic Ellipsometry, TEM and RBS/channeling techniques.

Photo-reflectance (PR) provides an optical means for rapid and precise measurement of near-surface electric fields in semiconductor materials. This paper details the use of photo-reflectance to characterize dopant activation in ultra-shallow junction (USJ) structures formed using millisecond anneal processes. USJ structures were formed in silicon using 500eV boron implantation with a dose of 1015/cm2, followed by flash anneals at 1250-1350°C. Reference metrology was performed using secondary ion mass spectroscopy (SIMS) and various sheet resistance (Rs) methods. Methods to calibrate photo-reflectance signals to active carrier concentration in USJ structures, including halo-doped samples, are described. Photo-reflectance is shown to be highly sensitive to active dopant concentration in USJ structures formed by millisecond annealing. Additionally, PR provides fast "on-product" measurement capability.

An important difference between monomer ion beams and heavy molecular beams is a significant reduction in beam angular divergence and increased on-wafer angular accuracy for molecular beams. This advantage in beam quality stems from a reduction in space-charge effects within the beam. Such improved angular accuracy has been shown to have a significant impact on the quality and yield of transistor devices [1,12]. In this study, B18Hx+ beam current and angular divergence data collected on a hybrid scanned beam line that magnetically scans the beam across the wafer is presented. Angular divergence is kept below 0.5 deg from an effective boron energy of 200 eV to 3000 eV. Under these conditions, the beam current is shown analytically to be limited by space charge below about I keV, but by the matching of the beam emittance to the acceptance of the beam line above I keV. In addition, results of a beam transport model which includes variable space charge compensation are presented, in which a drift mode B18Hx+ beam is compared to an otherwise identical boron beam after deceleration. Deceleration is shown to introduce significant space-charge blow up resulting in a large on-wafer angular divergence. The divergence effects introduced by wafer charging are also discussed.

High spatial resolution sheet resistance measurements, based on analysis of junction photo-voltage (JPV) signals, are used to reveal subtle dose uniformity variations for 40 and 90 keV Boron implants in the dose range of 10(11) B/cm(2). The use of various combinations of electrostatic ion beam scanning with linear and rotational wafer motion resulted in dose variations with patterns characteristic to the particular combination of scanning methods. Detailed wafer maps, based on over 70,000 pixel sites per wafer, were obtained with JPV methods for sheet resistances approaching 1 M-Ohm/square, providing for evaluation of local and global dose uniformity performance.

A non-contact method for measurement of sheet resistance and leakage current (RsL) for ultra-shallow junction (USJ) characterization is described based on analysis of frequency-dependent junction photovoltages from p-n junctions . Theoretical, device-simulated and measured photovoltages, sheet resistance as well as RsL and reverse-biased diode currents are compared. The linkage between RsL recombination currents and end-of-range implant damage in USJ/halo profiles and deletion layers is described. The addition of a Halo profile to a USJ results in increased in sheet resistance and leakage current due to changes in the junction depth and depletion layer conditions. Measured recombination leakage currents for implanted and CVD-grown USJs are compared with calculation and show good agreement.

Sheet resistance and leakage current of spike rapid thermal processed (RTP), millisecond flash (fRTP) annealed and chemical vapor deposition (CVD) grown ultra-shallow junctions (USJ) are compared with a non-contact junction photovoltage, RsL, technique. Theoretical reverse-biased diode and non-contact leakage currents are compared. A significant leakage current increase for spike RTP and fRTP processed USJ formed in halo-implanted profiles is described by high electron and hole recombination-generation in the end-of-range (EOR) damage layer enhanced by trap assisted and band-to-band tunneling. The reduced thermal budget of fRTP allows junction formation with reduced dopant diffusion and with lower sheet resistance. However when strong halo doping is employed, there is often a significant increase in junction leakage relative to that for junctions formed in lightly-doped test wafers. This increased leakage current can be reduced by annealing the halo implants before implanting the USJ or by lowering the halo dose. USJ grown with CVD demonstrate low leakage current due to localization of recombination centers at the edge of the depletion layer, where recombination (generation) is small. This study demonstrates the importance of characterizing USJ formed in halo profile for advanced ULSI.

Sheet resistance and leakage current density of spike rapid thermal processed, millisecond flash annealed, and chemical vapor deposition (CVD) grown ultrashallow junctions (USJs) are compared with the contactless junction photovoltage technique for measurement of sheet resistance and leakage current (RsL) and four-point probe (4PP) techniques. A significant leakage current increase for USJs formed in halo-implanted profiles is explained by high electron and hole recombination generation in the near-surface end-of-range damaged layer enhanced by trap-assisted tunneling. The reduced thermal budget of millisecond annealing allows junction formation with reduced dopant diffusion and lower sheet resistance. However, when strong halo doping is employed, there is a significant increase in junction leakage current relative to that for junctions formed by spike annealing. This rise in leakage current can be reduced by annealing the halo implants before implanting the USJ or by lowering the halo implant dose. USJs grown with CVD demonstrate low leakage current due to localization of recombination centers at the edge of the depletion layer where recombination (generation) is low. This study demonstrates the importance of characterizing USJs formed in halo profile using the contactless RsL technique and highlights the limitations of contact probes, such as four-point probes, for characterization of advanced ultralarge scale integrated junctions.