This work explores the characteristics of ferroelectric thin-film transistors (FeTFTs) utilizing an asymmetric dual-gate (DG) structure in both single-gate (SG) and DG operation modes. In the transfer characteristics, DG mode exhibits a memory window (MW) of 1.075 V, smaller than SG mode’s MW of 1.402 V, attributed to the back-gate bias effect causing a reduction in the device’s threshold voltage. However, DG mode demonstrates superior endurance characteristics with 106 cycles compared to SG mode’s 105 cycles. Additionally, the increase in erase pulse voltage (VERS) exacerbates the polycrystalline-silicon channel lattice damage of FeTFT, resulting in subthreshold swing (SS) degradation. Nevertheless, the extent of SS degradation from DG mode operation is significantly lower than that of SG mode, contributing to the superior endurance of DG mode. The elevation of program pulse voltage (VPRG) induces imprint and charge-trapping effects in the top-gate ferroelectric dielectric, leading to reduced endurance. Due to the use of SiO2 as the back-gate dielectric in FeTFT, DG mode exhibits lower impacts of charge-trapping effects from the top-gate ferroelectric dielectric layer, resulting in better endurance compared to SG mode. The asymmetric DG structure provides greater tolerance in the selection of VPRG and VERS.

In this work, CMOS-compatible antifuse HfO2 -based one-resistor and one-OTP (1R1O) nonvolatile memories (NVMs) were successfully fabricated and achieved a record-high pulsed memory window (MW) of 2x10(8) at a low read voltage of 1 V for the first time. By modulating the switching oxide thickness, the 1R1O NVMs with a 5 nm HfO2 tested under a crossbar memory array scheme can tolerate a write/read disturbance of 2x10(7)/10(9) cycles and show a robust 200 (degrees) C retention with an extremely stable pulsed MW of 2x10(8) after the read disturbance (RD) of 10(9 )cycles. According to pulsed characteristic and reliability viewpoints, the 5 nm HfO2 1R1O NVMs are very suitable candidates for Internet of Things (IoTs) and automotive (ATV) security integrated circuits (ICs).

The above article [1] presented data on microwave annealing of implanted ions in silicon. There are several typos in the figure captions and labels, and the authors would like to correct them. The text is correct, and the conclusion of [1] is not impacted by these revisions.

In this work, a ferroelectric tunnel thin-film transistor (FeT-TFT) with polycrystalline-silicon (poly-Si) channel and ferroelectric HfZrO x gate dielectric is demonstrated with analog memory characteristics for the application of synaptic devices. The FeT-TFT exhibits a much lower conduction current of ∼0.032 times in transfer characteristics and maximum conductance (G d ) of ∼ 0.14 to 0.2 times in potentiation and depression operation than the FeTFT due to FeT-TFT’s carrier transport mechanism: interband tunneling. This work employed pulse widths of 75, 150, and 300 ns to modulate G d , and it was found that using a pulse width of 75 ns could achieve low asymmetry ∼ 1 and high G d ratio ∼ 20.63 under the consideration of operation speed. When the pulse time is increased, the potentiation and depression voltages can be significantly decreased to maintain the low asymmetry, but the G d ratio is also reduced. In addition, the endurance characteristic of poly-Si FeT-TFT is found to be strongly related to the degradation effect of subthreshold swing due to the dynamic stress effect in the endurance measurement. This result reveals that the reliability of ferroelectric devices is not only owing to the degradation of the remanent polarization.

A 5-nm-thick HfO 2 anti-fuse one-time programmable (OTP) memory achieving a record-high pulsed memory window (MW) of $2.1\times 10^{8}$ at a low read voltage (V read ) of 1 V have been proposed and demonstrated for the first time. Furthermore, the HfO 2 OTP memory shows a robust 25°C retention with an extremely stable pulsed MW $> 2\times 10^{8}$ after 10 7 s. From the pulsed characteristics and reliability viewpoints, the HfO 2 OTP memory is a very suitable candidate for the Internet of Things (IoTs) applications and automotive (ATV) security integrated circuits (ICs).

The tunnel thin-film transistor (tunnel-TFT) with polycrystalline-silicon (poly-Si) channel and ferroelectric gate dielectric HfZrO x is fabricated to demonstrate the synaptic characteristics of potentiation and depression in conductance (G d ). Compared to conventional ferroelectric TFT (Fe-TFT), the ferroelectric tunnel-TFT exhibits much lower conduction current and G d due to its unique carrier transport mechanism: interband tunneling. The low conduction current and G d of ferroelectric tunnel-TFT can effectively reduce the power dissipation of neuromorphic computing circuits. Consequently, the ferroelectric tunnel-TFT is demonstrated to exhibit a 5-bit function, low asymmetry, and high G d ratio to meet the requirement of a high recognition rate of neuromorphic computing.

Thinning the thickness of the channel to the nanosheet structure effectively improves the control ability of the gate voltage to the channel potential to enhance the performance of the device and become the development direction of the device. Still, the influence on reliability degradation is mostly not considered simultaneously. This work investigates the effect of channel thinning on polycrystalline-silicon thin film transistors using nanosheet channel structures on device performance and reliability and finds that the degradation of device reliability is more severe with the thinning of nanosheet channels. The results present a reliability issue for particular improvement in the future development of nanosheet structures.

Monolithic 3D stacking of complementary FET (CFET) SRAM arrays increases integration density multi-fold while supporting the inherent SRAM advantages of low write power and near-infinite endurance. We propose stacking multiple 8-transistor CFET-SRAM layers on regular CMOS periphery to achieve an ultra-high-density array for computing-in-memory (CIM). CFET and regular CMOS (FinFET) devices are measured and calibrated with BSIM-CMG compact model. SPICE simulations are performed to evaluate the delay of CIM operation, power consumption, and analog computational error due to device non-linearity. The impact of device non-linearity on neural network inference accuracy is evaluated using the CIMulator simulation platform. Lower CFET current drive due to amorphous (deposited) silicon channel is shown to have negligible impact on CIM operational delay in many cases, as the maximum allowable current is limited by wiring resistance, not transistor drive strength while maintaining accurate weighted sum. Compared to regular 2D CMOS FinFET array. CFET SRAM cells show an improvement up to 57.19% in TOPS/W. Furthermore, the performance in TOPS/W mm 2 is improved up to $19\times $ . A factor proportional to the number of stacked layers for monolithically stacked CFET SRAM cells, makes it highly promising for future edge intelligence.

This work investigates the characteristics and reliability of double-gate (DG) and single-gate (SG) mode operations in polycrystalline-silicon nanosheet transistors (TFTs). It is observed that the threshold voltage and subthreshold swing in the DG mode are lower than those in the SG mode, while the on-state current is much higher. The DG mode provides better control over the channel potential, resulting in higher electron density and field-effect mobility. Moreover, the back-gate voltage can be used to adjust the threshold voltage of the TFT in SG mode. The impact of the back-gate voltage on the reliability of the device is also studied. The results indicate that the DG mode is more reliable than the SG mode under positive gate bias stress, as the DG mode has a stronger channel potential control ability. In contrast, the back-gate voltage has little effect on the reliability of the TFT in SG mode.

In this article, heterogeneous complementary field-effect-transistor (CFET) constructed by vertically stacking amorphous indium gallium zinc oxide (a-IGZO) n-channel on poly-Si p-channel with their own dielectric layer and work function metal gate inverters were demonstrated. Meanwhile, high-frequency IGZO radio frequency (RF) devices with poly-Si as guard ring material simultaneously were fabricated in the same process. High ${f}_{\text {T}}$ and ${f}_{\text {max}}$ IGZO Radio Frequency Integrated Circuits (RFICs) with the excellent on–off ratio need to be promoted by introducing fluorine-based gas. For the IGZO device in CFET, its threshold voltage can be tuned by the adjusted gate for ideal inverter operation at different supply voltage ( ${V}_{\text {DD}}$ ). Moreover, the swing of the IGZO transistor and the gain extracted from voltage transfer characteristic (VTC) curves can also be improved when the controlled gate and adjusted gate are connected as an input terminal, but the ${V}_{\text {TH}}$ tunability for the inverter is satisfied in the meantime. We also simulated 6T-SRAM circuit by SPICE model to further investigate the potential of an adjusted gate for optimizing the noise margin during SRAM operation.

This paper proposes an effective pretreatment process that combines wet ammonium sulfide ((NH4)(2)S) dipping and hydrazine (N2H4) vapor treatment before high dielectric constant (kappa, kappa) deposition to reduce native oxide and elemental arsenic (As) before atomic layer deposition of ammonium oxide (Al2O3) gate dielectrics on n-doped indium gallium arsenide (In0.7Ga0.3As) layers to form metal oxide semiconductor capacitors (MOSCAPs). X-ray photoelectron spectroscopy (XPS) analysis confirms that sulfuration of In0.7Ga0.3As surface by (NH4)(2)S solution dipping can effectively reduce indium-oxygen (In-O), gallium-oxygen (Ga-O), arsenic-oxygen (As-O) bonds while elemental As still exist at the high-kappa/In0.7Ga0.3As interface. Furthermore, N2H4 treatment on sulfurated In0.7Ga0.3As can effectively suppress the native oxides and elemental As. Accordingly, the obtained data indicate that the combination of chemical sulfur pretreatment and N2H4 treatment is advantageous to passivate the trap states on In0.7Ga0.3As metal-oxide-semiconductor capacitors (MOSCAPs). Moreover, forming gas annealing (FGA) process could further improve the capacitance-voltage (C-V) characteristics and the interface trap density (D-it) of In0.7Ga0.3As MOSCAP could be reduced significantly, achieving a value of 1.2 x 10(12) cm(-2) eV(-1).

Monolayer doping is a possible method for achieving complex-geometry structures with different semiconductors. Understanding the dopant diffusion behavior of monolayer doping, especially under different heating sources, is essential for further improvement. We examine and compare the doping profile and dopant activation with two different heating sources (rapid thermal annealing and microwave annealing), especially focused on SiO2/Si interface. These heating sources are used for junction diode fabrication, to realize current switching behavior. Direct observations of monolayer doping profiles, especially inside the capping oxide, are discussed to provide quantitative information for dopant concentration. This can provide significant information for better tuning of surface chemistries and process protocols applied in monolayer doping methodologies.

In this study, conventional CMOS and complementary field-effect transistor (CFET) inverters based on a vertically stacked-nanosheet (NS) structure were fabricated. The NS below 8-nm channel layer thickness (TSi) was obtained by dry etching and wet etching processes. The channel thickness is controlled by dry etching, and the channel width was shrunk down by wet etching. Compared to single nanowire field-effect transistors (NSFETs), stacked NSFETs exhibit higher ON-current performance. For the CMOS inverter, the voltage transfer characteristics (VTCs) could be matched much better by adjusting the channel widths and layers for N-channel MOSFET (NFET) and P-channel MOSFET (PFET), respectively. For the CFET inverter, layout areas could be reduced and requires less number of lithographic and ion implantation steps contrary to the CMOS inverter. However, we observe that the VTCs of the CFET inverters still show asymmetric behavior due to the difficulties of adjustment in NS layers and systematic behavior of threshold voltages for NFETs/PFETs. This work experimentally demonstrates the CMOS and CFET inverters on the vertically stacked NS structure, which is promising for system-on-panel (SoP) and 3-D-ICs applications.

In this paper, one proposed an effective method to enhance current drivability of junctionless FETs (JL-FETs) by utilizing uniaxial tensile strain effects. The strained layers were deposited on JL-FETs on silicon-on-insulator (SOI) and bulk Si wafers, respectively. Strained JL SOI FETs show an extremely low subthreshold swing (S.S.) of 65 mV/decade with I ON /I OFF > 10 9 ; strained JL bulk FinFETs show an S.S. of 75 mV/decade with I ON /I OFF > 10 7 . For strained JL bulk FinFETs, a triangular fin shape could suppress leakage current effectively. Regardless of substrates, JL FETs showed excellent performance owing to uniaxial tensile strain technology. Analysis of leakage current in strained JL FETs included effects on Gate-induced drain leakage trap-assisted tunneling effects were discussed by I D -V G curves under various temperatures and activation energy. Compared with JL SOI gate-all-around structures, JL bulk FinFET possesses higher I D and offer the promise of higher integration flexibility for Si CMOS compatible process for the future applications.

We focused on the damage-free monolayer doping (MLD) method starting from a chemical reaction of molecules on Si and Ge surfaces and applied it to 3D MOSFET device fabrication. MLD methods were verified by different material analysis, such as XPS and Raman spectroscopy. For a Si-based FinFET structure, compared to the device with ion implantation, the short channel effect of source and drain (SD) extension regions formed by MLD are improved. The shallower SD extension regions formed by low-temperature microwave annealing (MWA) are expected to the device showing better electrical properties than deeper ones formed by RTA. In addition, formation of the n- and p-type doping in Ge by MLD was also investigated. Even after annealing at 800 degrees C for 300 sec by RTA, the p-type doping still exhibits a low surface doping concentration due to the low diffusion coefficient of B in Ge and surface diffusion limitations at the MLD/Ge interface. By using a combination of RTA and CO2 laser spike annealing (LSA), MLD n-type doping in Ge are formed with junction depths of approximate to 15 nm, and peak concentration of approximate to 6 x 10(20) atoms/cm(3). The dopant activation for the MLD-doped channels of Ge junctionless FinFETs (JLFinFETs) is improved after the additional CO2 LSA. (C) 2017 The Electrochemical Society. All rights reserved.

A junctionless (JL) fin thin film transistor (FinTFT) with a novel shell doping profile (SDP) formed by a damage-free conformal molecular monolayer doping (MLD) method and a combination of microwave annealing (MWA) and CO 2 laser spike annealing (COLSA) is demonstrated and studied. MWA drives in and partially activates the MLD dopants; the resultant SDP features an ultra-shallow depth (<; 5nm) and an abrupt steepness (<; 0.8 nm/dec). The dopant activation of the devices experienced MLD and MWA is further enhanced by the nonmelting COLSA without dopant diffusion, and which can also avoid fin deformation and recover surface defects left by fin patterning. Thanks to the enhanced dopant activation by COLSA, the SDP-FinTFTs overall exhibit better performance than the SDP-FinTFTs without COLSA and the conventional implanted (imp) FinTFTs in terms of subthreshold swing (S.S.), on-currents (I on by 160% compared to the SDP-FinTFTs without COLSA) and on/off current ratio (I on /I off >10 7 ) for 3D stacked ICs applications. Our results reveal the potential of the proposed SDP formed by MLD, MWA and COLSA enabling a JLFinTFT showing excellent performance.

A novel silicide process with two-step low temperature microwave annealing (MWA) achieves NiSi thickness of 10 nm while maintaining low resistance, and an ultra-thin Ni silicide film, only 4.5 nm, has been realized. In this MWA system, we insert quartz and Si susceptors to change the absorption efficiency of the process wafer and provide fine turning in temperature control during annealing. The thickness of NiSi film is determined by microwave power and by changing the number and the position of quartz and Si susceptors in the first step of the anneal process. The STEM-HAADF combined EELS/EDS spectroscopies are used to analyze the electronic excitations and identify the phase of Ni silicide. (C) 2014 The Electrochemical Society. [DOI: 10.1149/2.006405jss] All rights reserved.

Low temperature microwave annealing (MWA) for IC processing is promising. In this study, using microwave annealing for dopant activation and thermal stability of the high-k/metal gate is investigated. Implanted species, such as phosphorus, arsenic, and boron, can also be well-activated and diffusionless in Si after microwave annealing. The flat band voltage shift of metal gate was suppressed due to the low temperature process. The increases in equivalent oxide thickness (EOT) of the MOS devices after dopant activation processing can be eliminated by using low temperature MW A. In addition, the short channel effects in n & pMOSFETs annealed by MW A can be also improved due to the suppression of dopant diffusion and stabilization of EOT.

Microwave annealing (MWA) and rapid thermal annealing (RTA) of dopants in implanted Si are compared in their abilities to produce very shallow and highly activated junctions. First, arsenic (As), phosphorus (P), and BF2 implants in Si substrate were annealed by MWA at temperatures below 550 degrees C. Next, enhancing the substitutional carbon concentration ([C] sub) by cluster carbon implantation in (100) Si substrates with MWA or RTA techniques was investigated. Annealing temperatures and time effects were studied. Different formation mechanisms of SiCx layer were observed. In addition, substrate temperature is an important factor for dopant activation during MWA and in situ doped a-Si on oxide/Si substrate or glass were compared to elucidate the substrate temperature effect. After the discussion of dopant activation in Si substrates, low temperature formation of ultrathin NiGe layer is presented. Ultrathin NiGe films with low sheet resistance have been demonstrated with a novel two-step MWA process. In the two-step MWA process, the first step anneals the sample with low power MWA, and the second step applies higher power MWA for reducing sheet resistance. During fixed-frequency microwave heating, standing wave patterns may be present in the MWA chamber resulting in nodes and antinodes and thermal variations over the process wafer. Therefore, the effects of Si or quartz susceptor wafers on dopant activation and sheet resistance uniformity during fixed-frequency MWA were investigated.