This 390mm/sup 2/ 16-bank 1Gb double-data-rate synchronous DRAM (DDR SDRAM) includes: (1) hybrid-bitline architecture; (2) hierarchical column-select operation; (3) hierarchical 8b prefetch; and (4) 1V swing single-ended read-write-drive (RWD) circuitry.
Toshiaki Kirihata合作论文数IBM Systems and Technology Group, Semiconductor Research and Development Center, 2070 Route 52, Hopewell Junction, NY 12533, USA4
john ross合作论文数2
Gerhard Mueller合作论文数2
Brian L Ji合作论文数2
Heinz Hoenigschmid合作论文数2H. Terletzki合作论文数1m selz合作论文数1L. Hsu合作论文数1FRANKOWSKY G合作论文数1peter poechmueller合作论文数1gabriel daniel合作论文数1
Daniel W. Storaska合作论文数1M. A. Hug合作论文数1A. M. Reith合作论文数1K. P. Guay合作论文数1Matthew R Wordeman合作论文数1O. Weinfurtner合作论文数1
