A 7F/sup 2/ DRAM cell and corresponding vertically folded bitline architecture has been fabricated using a 0.175 /spl mu/m CMOS technology. This concept features an advanced 30/spl deg/ tilted array device layout and an area penalty free inter BL twist. The presented scheme minimizes local well noise by maximizing the number of twisting intervals.

This 390mm/sup 2/ 16-bank 1Gb double-data-rate synchronous DRAM (DDR SDRAM) includes: (1) hybrid-bitline architecture; (2) hierarchical column-select operation; (3) hierarchical 8b prefetch; and (4) 1V swing single-ended read-write-drive (RWD) circuitry.

This paper presents a detailed study on the impact of floating body in partially-depleted (PD) SOI MOSFET on various digital VLSI CMOS circuit families. The parasitic bipolar effect resulting from the floating body is shown to degrade the circuit noise margin and stability in general. In certain dynamic circuits and wide multiplexers, the parasitic bipolar effect is shown to cause logic state error if not properly accounted for.

This paper presents a study of sub-0.25-mu m CMOS SRAM bitline circuitry on partially depleted (PD) silicon-on-insulator (SOI) technology. SOI implementations outperform conventional bulk ones due to significant reduction of collective device junction capacitance on the bitlines. Floating body effects are investigated for both read and write cycles, Array content dependent behaviors are identified for the first time and analyzed with worst-case temporal and spatial pattern combinations.