An brief overview is given of the voltage generator system of a 1-Gb synchronous DRAM. The design serves as an example for a state-of-the-art DRAM voltage generator system. A general analysis of the required controlling functionality is derived. A universal and flexible controlling scheme for a voltage generator system is presented, which can easily be modified for future voltage generator design. The main aspect of this controlling scheme is a clear separation between logic (digital) controlling functions and (analog) voltage generating functions. A control path that supplies the various voltage generator blocks with configuration information is introduced. Last, the control path is shown to have an additional advantage of increased testability. Hardware results verifying the concept are presented.

A 7F/sup 2/ DRAM cell and corresponding vertically folded bitline architecture has been fabricated using a 0.175 /spl mu/m CMOS technology. This concept features an advanced 30/spl deg/ tilted array device layout and an area penalty free inter BL twist. The presented scheme minimizes local well noise by maximizing the number of twisting intervals.

This 390mm/sup 2/ 16-bank 1Gb double-data-rate synchronous DRAM (DDR SDRAM) includes: (1) hybrid-bitline architecture; (2) hierarchical column-select operation; (3) hierarchical 8b prefetch; and (4) 1V swing single-ended read-write-drive (RWD) circuitry.

A 220-mm/sup 2/, 256-Mb SDRAM has been fabricated in fully planarized 0.22-/spl mu/m CMOS technology with buried strap trench cell. The single-sided stitched word-line (WL) architecture employs asymmetric block activation and shared row decoders to realize 86.7% cell/chip-length efficiency (57.3% cell/chip efficiency). A staggered WL driver arrangement makes it possible to build the drivers on a 0.484-/spl mu/m WL pitch in limited space. An intraunit address increment pipeline scheme having two logical 8-Mb arrays within one physical 16-Mb unit results in a burst frequency up to 200 MHz for single data rate, while allowing four- and eight-bank organizations. A data rate of 270 Mbits/s was confirmed with a 135-MHz frequency doubling test mode. Single-ended addresses and a single ended read-write-drive bus reduce the ICC/sub 4/ current to /spl sim/90 mA for 100-MHz seamless burst operation. A detailed shmoo analysis demonstrates address-access time of 13.5 ns and clock-access time of 5 ns. This design also uses a selectable row domain and divided column redundancy scheme that repairs up to /spl sim/1400 faults/chip with only 8% chip overhead.