This work presents a single-channel, fully dynamic pipelined-SAR ADC with relaxed architectural tradeoffs thanks to the use of ring amplification and background calibration. It leverages a novel SAR quantizer and narrowband dither injection to achieve fast and comprehensive background calibration of DAC mismatch, interstage gain, and ring amplifier (ringamp) linearity and bias optimality. The ADC also includes an on-chip, wide-range, fully dynamic reference regulation system. Implemented in 16-nm CMOS, it consumes 3.3 mW at 500 MS/s (including regulation) and achieves 10.1 ENOB and 75.5-dB SFDR, resulting in Schreier and Walden figure-of-merit (FoM) values of 171.1 dB and 6.2 fJ/conv.-step, respectively.

A background calibration algorithm is proposed for comparator offsets and thresholds, and for DAC gains. It leverages redundancy in a 2-step ADC to detect errors without the need for additional analog blocks. The algorithm considers an error to have occurred when the fine phase outputs a result within its redundant range. The detected errors are classified into possible erroneous comparisons, and the source of the error is estimated by analyzing the error occurrence pattern. It has been implemented off-chip for a 4× time-interleaved Ping-Pong SAR ADC, which demonstrates the tolerance for ±8% VDD variation and convergence within 180k samples after a sudden 5% VDD drop.

A 4× interleaved pipelined ADC for direct-RF sampling applications is presented. It leverages the performance advantages of ring amplifiers to unlock greater architectural freedom. The first pipeline stage MDAC with a “passive-hold” mode eliminates the sub-ADC sampling path and associated problems. A high-speed ringamp topology employs digital bias control, robust common-mode feedback (CMFB), and an elegant self-resetting behavior. An asynchronous, event-driven timing control system improves several aspects of performance and enables fully dynamic power consumption and modular design re-use. A general technique is presented whereby the signal-to-distortion ratio (SDR) of any amplifier in the system can be measured in the background with an analog hardware overhead of only one comparator. In this amplifier-intensive architecture utilizing 36 ringamps, the 4-GS/s ADC fabricated in 16-nm CMOS achieves 62-dB SNDR and 75-dB SFDR at Nyquist, consumes 75 mW (including input buffer), and has a Walden figure of merit (FoM) of 18 fJ/conversion-step and a Schreier FoM of 166 dB, advancing the state of the art in direct-RF sampling ADCs by roughly an order of magnitude.

We present a time-interleaved (TI) SAR ADC with 8 channels realizing 8-bit conversion at 1 GS/s each. SNDR is 45 dB at low frequency with an ERBW of 5 GHz limited by sampler distortion. Conventional SAR conversion at high speed with minimum degradation is achieved by leveraging techniques such as early quantization, minimum delay logic, DAC redundancy and gain and offset compensation via the DAC. At 8 GS/s the ADC consumes 26 mW resulting in an efficiency of 30 fJ/conv.-step.

An asynchronous event-driven approach to clocking and timing control is explored in the context of pipelined ADCs. It is shown how a conventional global clock tree can be replaced by localized control units coordinated through inter-stage communication protocols. The approach is found to yield many compelling advantages in terms of power efficiency, speed, robustness, and reconfigurability. It is shown how these benefits are particularly well leveraged when used in combination with dynamic-power residue amplifiers such as ring amplifiers. Several challenges also arise: re-synchronization of the digital outputs, mitigation of possible deadlock scenarios, and robust timing control configuration. Solutions to these problems are presented. Two single-channel 11-bit 1.5-bit/stage pipelined ADC designs are fabricated in a 16nm CMOS technology, each with a different implementation approach to the asynchronous control units. The trade-offs of both approaches are considered. At 1 GS/s the fastest prototype achieves 59.5 dB SNDR and 75.9 dB SFDR at Nyquist, consuming 10.9 mW including reference regulator. Due to fully-dynamic operation, it maintains a near-constant Walden Figure of Merit (FoM) of 14 fJ/conversion-step from 1 MS/s to 1 GS/s.

We present a single-channel fully-dynamic pipelined SAR ADC that leverages a novel quantizer and narrowband dither injection to achieve fast and comprehensive background calibration of DAC mismatch, interstage gain, and ring amplifier (ringamp) bias optimality. The ADC also includes an on-chip wide-range, fully-dynamic reference regulation system. Consuming 3.3 mW at 500 MS/s, it achieves 10.0 ENOB and 75.5 dB SFDR, yielding a Walden FoM of 6.2 fJ/c.s.

This article presents a fully dynamic ringamp-based pipelined ADC with integrated reference buffer that operates from 1-MS/s to 1-GS/s and maintains a Walden Figure-of-Merit (FoM) of 14 fJ/conversion-step across this range. A “split-reference” regulation technique is introduced, which provides multiple buffered replicas with varying accuracies and output impedances to the core ADC circuitry, relaxing overall buffer design requirements and improving efficiency. The regulator blocks are implemented with fully dynamic discrete-time loops. Furthermore, a technique for background reconstruction of residue amplifier settling behavior is also described. The “scope-on-chip” captures high-resolution transient waveforms using a 1-bit stochastic ADC. It is shown how these waveform data can be used for optimization of ringamp biasing and PVT tracking. The ADC is fabricated in a 16-nm CMOS technology and at 1 GS/s with a Nyquist input achieves 59.5-dB SNDR, 75.9-dB SFDR, and 10.9-mW total power consumption with only 8% consumed by the reference regulation.

This paper presents an 11 bit fully dynamic pipelined ADC with an integrated reference buffer that consumes only 8% of total power. It operates from 1MS/s to 1GS/s and maintains 59.5dB SNDR and 14fJ/conv-step FoM W across this range. Furthermore, a small circuit is introduced that provides background reconstruction of amplifier settling behavior.

This letter introduces a novel SAR-based algorithm that speeds up the conversion by using two digital-to-analog converters that operate in a ping-pong fashion. It has been implemented in a $4\times $ time-interleaved analog-to-digital converter in a 16-nm FinFET technology. Each channel uses the proposed ping-pong SAR (PP-SAR) algorithm in a coarse phase followed by a comparator-based asynchronous binary search (CABS) fine phase to realize 418 MHz/channel 10-bit conversion with 51-dB SNDR at Nyquist. The total power consumption is 7.9 mW corresponding to a Walden FoM of 16 fJ/conversion-step at Nyquist.

Giga-sample ADCs targeting high performance communication applications such as direct-RF sampling all rely on some form of residue amplification to minimize the number of interleaved channels and meet demanding specifications. Despite architectural efforts to reduce the total number of amplifiers in the system, the challenges associated with designing them for high bandwidth and linearity has limited reported power efficiencies [1]. In this work, we show that ring amplification [2] can overcome this longstanding bottleneck. In an architecture using 36 ringamps, the 3.2GS/s ADC consuming 61.3mW has a Nyquist SNDR of 61.7dB, SFDR of 73.3dB, Walden FoM of 19.2fJ/conv-step, and Schreier FoM of 165.9dB. Furthermore, we demonstrate a general technique whereby the signal-to-distortion ratio (SDR) of any amplifier in the system can be independently monitored in the background with an analog hardware overhead of only one comparator.

At the upper end of achievable ADC operating speeds, clocking becomes a critical performance limiter. In “deep” pipelined ADCs that contain many stages, the clock tree constitutes a highly distributed network, with parasitics and mismatch creating skew between the different branches. Sufficient margin must be included in the timing generation such that all non-overlap and causal relationships are maintained. This leads to a difficult set of design tradeoffs in terms of power, speed, jitter, and reliability. Meanwhile, although residue amplifiers have traditionally dominated the power budget in deep pipelines, recent advances such as ring amplification have improved achievable efficiencies to the point that clocking is now the primary consumer in some cases [1, 2].

This paper presents a 2×14bit cartesian Direct Digital RF Modulator (DDRM) in 28nm CMOS. Both AM and PM calibration circuits are introduced to relax matching requirements of the DDRM units which results in a compact and efficient implementation. The DDRM features a memoryless current source based unit cell to avoid complex dynamic digital predistortion (DPD) algorithms. All the units can be tuned to less than 0.4LSB from their nominal value. When combined with memoryless DPD, ACLR and C-IM3 better than -60dBc is obtained at ~0dBm output power.

This paper reports a 15 GHz quadrature voltage controlled oscillator (QVCO) designed in a 130 nm CMOS technology. The phase noise performance of the QVCO and of a phase locked loop (PLL) where the QVCO was inserted were compared with the literature and with telecom standards and commercial products for broadcast satellite applications.

An inductorless, divide-by-256 fixed-modulus digital frequency divider with programmable input sensitivity, fabricated in 130 nm CMOS bulk process, is presented. Both the absence of inductors and the architecture used allow to obtain a small sized chip. The fabricated frequency divider exhibits two minima in sensitivity at 4.4 GHz and 6.25 GHz consuming about 5.4 mW from a 1.2 V voltage supply. The total active area of the frequency divider is 360 × 115 ¿m2.