This paper proposes a novel synergistic doping combined with morphology engineering (SDME) technique to reduce parasitic gate capacitance (C-gg) in vertical channel transistors (VFETs). The SDME approach synergistically integrates epitaxial in-situ doping, solid-state source diffusion, and atomic layer etching (ALE) to reconstruct the source-drain extension (SDE) region in three dimensions. It achieves a substantial reduction in parasitic C-gg while simultaneously delivering a higher on-state current (I-on) compared to the conventional VFET with inner spacer scheme. Firstly, we identified the key design parameters and optimized the channel shape of the proposed scheme. Secondly, a multi-objective optimization (MOO) was performed, balancing the I-on against the C-gg through numerous TCAD simulations. Finally, in 15-stage ring oscillator (RO), it not only matches the performance of a nitride (kappa = 7.9) sidewall across various loads but also, under a heavy load condition, nearly attains the performance level set by the low-kappa (kappa = 3.3) inner spacer.

In this paper, we propose a novel n-type body-contacted vertical channel field-effect transistor (BCVFET) with low gate-induced drain leakage (GIDL) and widely tunable threshold voltage and on-current. By connecting a horizontal body directly to the vertical nanosheet channel, the off-state leakage is suppressed by more than 80%. Through optimization of device geometry parameters, the remaining leakage is further reduced by 90%, while achieving a Vt shift of -0.37 V/V and an approximately 20% increase in Ion (at Vg = 2 V) as Vb is tuned from -0.5 V to 0.5 V. An n-type BCVFET structure was fabricated using a conventional CMOS process flow based on optimized simulation parameters. The process included Si/SiGe/Si/SiGe/Si epitaxy, side layer diffusion (SLD), and metal gate etch-back. SADP and EDS analyses confirmed the formation of a single-crystalline channel and an integrated body structure, respectively. These results demonstrate a promising approach to realizing a 4F2 architecture for future DRAM integration, particularly leveraging its low leakage current and tunable Vt and on-current.

In this work, the significant impact of asymmetric source/drain parasitic resistance on hot-carrier degradation (HCD) in n-type vertical nanosheet field-effect transistor (VNSFET) is systematically investigated. The parasitic source and drain resistances are extracted using the channel resistance method (CRM) and the constant current method, showing a bottom-to-top resistance ratio of approximately 3:1. Under the normal-mode (with the top terminal as the drain), HCD exhibits a power-law degradation trend, in contrast to the obvious saturation behavior under the reverse mode (with the bottom terminal as the drain). TCAD simulations demonstrate that such resistance asymmetry redistributes the internal voltages: a high lateral field causes channel hot-carrier (CHC) degradation in normal-mode, while the voltage drops across the large top resistance in reverse mode induces a parasitic positive bias temperature instability (PBTI) by the vertical electrical field. This work clarifies the role of parasitic resistance in determining the dominant degradation mechanism in inevitably asymmetric 3-D device architectures, providing key insights into reliability-aware optimization for vertical transistors in next-generation high-density memory and computing systems.

Molybdenum disulfide MoS2 is an attractive solid lubricant because weak interlayer interactions enable easy shear, yet its wear resistance deteriorates at low temperatures. Ti doping serves as a microstructural design strategy to strengthen MoS2 for cryogenic service. Experiments and simulations show that dispersed Ti modifies local bonding, induces Ti-S coordinated configurations, and builds an interlayer network of Ti, S, and Ti-S clusters. This nanoscale architecture raises hardness to 1.93GPa and elastic modulus to 45.30GPa through lattice distortion and strong pinning that hinder interlayer shear. Although the strengthened interface increases the friction coefficient, it markedly lowers wear at 223K. Atomistic simulations reveal a transition from progressive interlayer sliding and local delamination in pristine MoS2 to coherent block-like deformation of pinned layers, which promotes more uniform stress accommodation. The associated increase in bending stiffness also suppresses wrinkling, offering a clear design route for durable solid-lubricant coatings in low-temperature environments.

We demonstrate a novel n-type dual vertical C-shaped-channel nanosheet field-effect-transistor (dVCNFET) with ultra-thin channels, featured by self-aligned and replaced high-kappa metal gates aiming at high-performance logic circuits. The dVCNFETs were fabricated by high-quality Si/SiGe/Si epitaxy, Si epi growth on SiGe and SiGe bidirectional cross etching method, enabling precise control over channel thickness (T-channel), gate length and self-aligned gate formation. The space between channels were controlled by etch but not lithography, which means that the space can also be well controlled at advanced technology. This fabrication method is complementary metal oxide semiconductor technology compatible and nanosheets with T-channel < 3 nm were obtained. Moreover, the device exhibits excellent performance and gate control, with I-on = 204 mu A mu m(-1) (@ V-GS-V-T = 1 V, V-DS = 0.65 V), I-on/I-off = 8.69 x 10(8), SS = 61 mV dec(-1) and DIBL = 17 mV V-1.

In this article, the influence of Forming Gas Annealing (FGA) on the Positive Bias Temperature Instability (PBTI) characteristics of n-vertical C-shaped-channel nanosheet FET (n-VCNFET) is studied. The experimental results show that the extra FGA can significantly suppress both the initial and generated interface traps in PBTI. Moreover, in ultra-fast PBTI the pre-existing trap and total trap of VCNFET due to FGA decreases by 35 % and 31 %, respectively. The energy level of the oxide trap under PBTI and recovery doesn't change, in other words, the FGA induces the oxide trap density of the devices to decrease by 36 % at 125 degrees C and 1.4 V VOV. The optimization effect of FGA annealing has been further confirmed from the perspective of trap generation. It provides a guideline for the PBTI improvement of VCNFET in trap scopes.

This paper presents a comprehensive study of silicon germanium (SiGe) cladded channels for stacked nanowires (NWs), focusing on morphological control and strain engineering to enhance device performance. High-resolution transmission electron microscopy (TEM) was used to characterize the Si NWs and SiGe cladding morphology. The results demonstrate that the morphology of SiGe cladding can be controlled by adjusting the high-temperature H2 baking conditions, leading to shapes such as triangular, circular, and hexagonal. Technology computer-aided design simulations and geometric phase analysis of TEM images revealed that the maximum compressive stress of SiGe cladding is 3 GPa, corresponding to a compressive strain of 2.48%, which significantly enhances hole mobility. Electrical performance tests and simulations on p-type metal–oxide–semiconductor field-effect transistor devices with different morphologies showed excellent short-channel effect control, with a subthreshold swing (SS) of approximately 70 mV/dec and a drain-induced barrier lowering of only 40 mV/V. These findings provide valuable guidelines for fabricating high-quality SiGe channels with controlled structures, enabling the realization of high carrier mobilities in future devices.

Poly-Si nanosheet FETs (NSFETs) with vertical C-shaped channel are experimentally demonstrated using pulse layer crystallization. The vertical channel shows Si (110) plane and better crystallization is accomplished using exposed-drain integration strategy. The poly-Si NSFETs have SS of 67.5 mV/decade, I-OFF of 4.6 pA/mu m, and I-ON/I-OFF of 6.2x10(6). The present process provides a new pathway for upper device fabrication in monolithic 3D (M3D) technology.

In order to study the coupling mechanism of the process parameters during the double-glow discharge process, and thus to enhance the theoretical study of double-glow plasma surface metallurgical technology, in this paper, a two-dimensional fluid model is established using COMSOL simulation software. The effects of key processing factors on the distribution of electrons and excited argon ions, potential and electron temperature in the coupling process of double-glow discharge were investigated. The results indicated that the electron density between the two electrode plates increases as the voltage difference increases. The optimal working pressure was kept between 0.14 Torr and 0.29 Torr. The optimal electrode spacing was between 15 mm and 30 mm and decreased with the increase in pressure. Compared with the actual plasma surface alloying process experiment, the simulation results were consistent with the experiments. The research can guide experiments by combining simulation and theory, and the predictability and accuracy of double-glow surface metallurgy technology have been improved.

A common source p-type single-crystal channel three-dimensional ferroelectric field-effect transistor (3D FeFET) in a 2×2×3 array is proposed. Two programming and erasing conditions are introduced. A large memory window (> 1.2 V), good retention (>10 years), and high speed (<100 ns) was presented under high voltage (±6 V) conditions. The endurance，>103, was observed under relatively low voltage (±3 V) conditions. Based on these two conditions, a novel asymmetric bias program and erase method is proposed to obtain good disturb inhibition. A more than 0.5 V threshold voltage shift in target cell was achieved while threshold voltage shift in unselected cell was limited, and analysis of long term disturb in novel method is proposed, showing good disturb inhibition. Additional investigation in word line disturbance shows causation and efficiency of disturb. Building upon the proposed structure of the 3D FeFET array, a vector matrix multiplication able to calculate 2-bit weights was designed and demonstrated. This work provides a potential solution for increasing integration density with 3D FeFET array.

High-performance vertical-channel flash (HVF) memory cells were fabricated on the single crystalline Si (c-Si) sidewalls of the cylindrical deep wells in c-Si substrate. To investigate the diameter effects of the cylindrical deep wells, namely channel holes, on HVF cells, the channel holes with different diameters, ranging from 65 nm to 260 nm, were made. Memory gate stacks of SiO2/Al2O3/HfO2/Al2O3/TiN/W were formed by ozone oxidation and then ALD with the deposition thicknesses of 1/5/7/8/2/150 nm, respectively. For the devices with their diameters equal to or greater than 150 nm, their electrical properties, such as Vt, SS, DIBL, and program/erase characteristics, are close. As expected, DIBL and SS become better as the diameter increasing due to better gate control with larger diameter. However, large changes were occurred for the devices with the diameters of 90 nm and 65 nm. A simple model based on cylinder bulk for vertical flash memory devices was presented to obtain an approximate analytical solution for depletion-width and explain our experimental data. For the devices with the diameters of 150 nm, the high On/Off current ratio of 107 and relatively large memory window of 4.5 V were achieved. However, programming/erasing efficiency were degraded with hole diameter decreasing.

A new type of vertical sandwich gate-all around tunneling field-effect-transistors (TFETs), called VSATFETs, was demonstrated firstly with a CMOS-compatible process. The VSATFETs with self-aligned high-κ metal gates (HKMG) and abrupt doping tunneling junctions were fabricated with the epitaxial of p+−Si/i-SiGe/n+−Si sandwich structure and an isotropic quasi-atomic layer-etch (qALE) process. VSATFETs have the advantage of excellent control of channel size, because its gate-length is mainly determined by the thickness of SiGe film grown by epitaxy, and the diameter of the nanowires (NWs)/thickness of nanosheets (NSs) is determined by the qALE etching of SiGe selective to Si. A NW VSATFET with a diameter of 18 nm was fabricated and exhibits excellent characteristics: SS min = 61.64 mV dec −1 , I on = 2.25 × 10 −7 A u −1 m −1 (@V gs −V t = 0.45 V, V d = 0.65 V), I on /I off = 1.81 × 10 6 , DIBL = 7.58 mV. The effect of interface traps on the device performance was analyzed by the calibrated model. It is found that the device performance can be improved by decreasing the thickness/diameter of NS/NW TFET.

At sub-3 nm nodes, the scaling of lateral devices represented by a fin field-effect transistor (FinFET) and gate-all-around field effect transistors (GAAFET) faces increasing technical challenges. At the same time, the development of vertical devices in the three-dimensional direction has excellent potential for scaling. However, existing vertical devices face two technical challenges: “self-alignment of gate and channel” and “precise gate length control”. A recrystallization-based vertical C-shaped-channel nanosheet field effect transistor (RC-VCNFET) was proposed, and related process modules were developed. The vertical nanosheet with an “exposed top” structure was successfully fabricated. Moreover, through physical characterization methods such as scanning electron microscopy (SEM), atomic force microscopy (AFM), conductive atomic force microscopy (C-AFM) and transmission electron microscopy (TEM), the influencing factors of the crystal structure of the vertical nanosheet were analyzed. This lays the foundation for fabricating high-performance and low-cost RC-VCNFETs devices in the future.

Transistor scaling has become increasingly difficult in the dynamic random access memory (DRAM). However, vertical devices will be good candidates for 4F(2) DRAM cell transistors (F = pitch/2). Most vertical devices are facing some technical challenges. For example, the gate length cannot be precisely controlled, and the gate and the source/drain of the device cannot be aligned. Recrystallization-based vertical C-shaped-channel nanosheet field-effect transistors (RC-VCNFETs) were fabricated. The critical process modules of the RC-VCNFETs were developed as well. The RC-VCNFET with a self-aligned gate structure has excellent device performance, and its subthreshold swing (SS) is 62.91 mV/dec. Drain-induced barrier lowering (DIBL) is 6.16 mV/V.

A special Ge nanowire/nanosheet (NW/NS) p-type vertical sandwich gate-all-around (GAA) field-effect transistor (FET) (Ge NW/NS pVSAFET) with self-aligned high-κ metal gates (HKMGs) is proposed. The Ge pVSAFETs were fabricated by high-quality GeSi/Ge epitaxy, an exclusively developed self-limiting isotropic quasi atomic layer etching (qALE) of Ge selective to both GeSi and the (111) plane, top-drain implantation, and ozone postoxidation (OPO) channel passivation. The Ge pVSAFETs, which have hourglass-shaped (111) channels with the smallest size range from 5 to 20 nm formed by qALE, have reached a record high Ion of ∼291 μA/μm and exhibited good short channel effects (SCEs) control. The integration flow is compatible with mainstream CMOS processes, and Ge pVSAFETs with precise control of gate lengths/channel sizes were obtained.

We presented and demonstrated both n- and p-type vertical C-shaped-channel nanosheet field-effect transistors (VCNFETs) featured with precise control of both channel thickness and gate length. The VCNFETs were fabricated by high-quality Si/SiGe epitaxy and atomic layer deposition to obtain nanometer-scale process control and self-aligned high- ${k}$ metal gate (HKMG). The integration flow is compatible with the process used in the mainstream industry and it can be easily extended to vertically stacked devices. Both the gate length and the channel thickness of the VCNFETs are mainly determined by the thicknesses of Si/SiGe films grown by epitaxy, instead of lithography and etch techniques. Perfect subthreshold swing (SS), small drain-induced barrier lowering (DIBL), and large ${I}_{ \mathrm{\scriptscriptstyle ON}}/{I}_{ \mathrm{\scriptscriptstyle OFF}}$ ratio were achieved for both n- and p-VCNFETs due to the crystalline silicon channel and the well-defined doping profiles. The device performance and optimization were also investigated and discussed. Used as access transistors in dynamic random access memory (DRAM) array, VCNFETs were also demonstrated for the potential applications to 10-nm DRAM and beyond.

In this paper, we describe several scaling challenges of SRAM consisting of FinFETs and horizontal Gate-All-Around (GAA) Nano-sheet Field-Effect-Transistors (NshFETs), especially investigations related to Design-Technology Co-Optimization (DTCO). Comb-shaped channel FETs (CombFETs), which integrates the advantages of FinFETs and NshFETs were introduced to a six-transistor (6 T) SRAM cell and the corresponding simulations were established. The results show that compared with both FinFETs and NshFETs, CombFETs have larger the effective channel width or higher current at the same footprint and larger room for improving the mobility mismatch between N/P transistors. Moreover, CombFET SRAM showed ∼55% increase in effective channel width, 15% improvement of read static noise margin, ∼25% write speed gain, 88% read speed gain or 20% decrease in the minimum operating voltage (Vmin).

A novel comb-like-channel field-effect transistor (CombFET), which is the combination of the fin field-effect transistor (FinFET) and nanosheet FET (NshFET) geometries in the channel region, is proposed and evaluated numerically for the first time. Our simulations show that: 1) with the same footprint, CombFET ON-current is 43% higher than FinFET and 53% higher than gate-all-around FET (GAAFET) due to its larger effective channel width and relieved channel quantum confinement and 2) CombFETs have great advantages in performance optimization through surface orientation over FinFETs and NshFETs. Thanks to the unique structural design, CombFET can also be used to improve or eliminate the bending or adhesion effects between nanosheets/comb teeth.

Ferroelectric vertical gate-all-around field-effect-transistor (Fe-VGAAFET) suits a memory cell with a 5 nm technology node and beyond since it is less constrained by gate length, thereby providing sufficient space for the ferroelectric film compared with ferroelectric FinFET (Fe-FinFET) and ferroelectric lateral gate-all-around field-effect-transistors (Fe-LGAAFET). Also, Fe-VGAAFET achieves multilayer vertical stacking, which further increases the integrated density of devices. Here, we develop ferroelectric vertical sandwich gate-all-around field-effect-transistors (Fe-VSAFETs) with large memory windows (the maximum 2.3 V), high program/erase speeds (100 ns), and excellent retention properties using a self-aligned high- $\kappa $ metal gate process. Furthermore, vertical nanosheet devices with two channel thicknesses of approximately 16 and 42 nm and nanowire devices with a channel diameter of 30 nm were successfully fabricated, and excellent device characteristics were obtained.