This paper presents an integrated IR-Informed Timing and Timing-Aware IR Optimization flow with an IR-drop predictor. The proposed flow couples an IR-Informed Timing Optimizer with a Timing-Aware IR Optimizer to consider the mutual impact between IR-drop and timing during optimization. Then, we leverage a fast ML-based IR-drop predictor to quickly estimate the IR-drop after each iteration of optimization, which enables fast switching between the IR optimizer and timing optimizer. We further propose Feature Approximation to speed up the inference time of the IR-drop predictor. On two 7nm designs, the proposed flow closes timing and eliminates at least 90.6% of IR-drop violations. The Feature Approximation achieves 67% speed up in the runtime of the overall flow. Our optimization flow can be applied to a 945k-cell design with 7,578 IR-drop violations within 3 hours, demonstrating its practicality.
Dynamic Deep Neural Networks (D2NNs) with early exits have emerged as an effective architecture for reducing computational overhead and inference latency. While fault tolerance in their static counterparts has been extensively studied, the dynamic models remain largely unexplored for enhanced reliability. This paper addresses that gap by developing Bayesian optimization algorithms to determine optimal early-exit confidence thresholds for enhanced fault resilience in dynamic DNNs. We present a reliability assessment of BranchyNet models compared to their static counterparts across three state-of-the-art architectures, introducing random bit flips (up to 0.01% of total model parameters) across 11 logarithmically increasing Bit Error Rates (BERs). The study analyzes fixed and adaptive thresholds that dynamically adjust considering the estimated fault rates. The results demonstrate that BranchyNet models exhibit greater fault resilience, preserving accuracy even at BER levels up to 2x higher than those tolerated by static models, with adaptive thresholds providing the strongest resilience. By combining exit threshold tuning with multiple inference pathways, early-exit DNNs offer a practical means to mitigate radiation-induced soft errors in hardware deployments.
Stochastic computing (SC) is an approximate computing that represents numerical values based on the probability of ones in bitstreams and performs operations probabilistically. Arithmetic circuits for SC (SC circuits) have attracted attention for applications such as machine learning and image processing due to advantages like not only low area and power consumption but also high fault tolerance. To accelerate stochastic computing based on linear finite state machines (FSMs), parallel implementation of linear FSMs has been proposed. The first objective of this paper is to analyze this parallel implementation method and to clarify the details of the design and the cost-effectiveness of the parallel implementation. Through this analysis, it is shown that hardware cost can be significantly reduced while maintaining high accuracy. As the second objective, this paper proposes a new method of parallel implementation using multi-input linear FSMs in order to further improve the accuracy. Experimental results show these proposed designs can achieve high accuracy while keeping the area and delay low.
Static learning has been used to improve structural Automatic Test Pattern Generation (ATPG) results by reducing backtracks and thus aborted faults. However, static learning is limited to simple relationships and can generate massive learning data, most of which is not needed during ATPG. We present a new dynamic learning technique to learn only needed relationships that can include multiple gates and time frames. We show improved coverage and pattern count on industrial design.
As the demand for Semiconductor Devices used in varied applications, such as consumer electronics to automotive, to aerospace, increases exponentially, more and more silicon wafers and packaged chips need to be tested before delivery. The key role of testing is to ensure that the semiconductor devices are free from any defects and meet all the required specifications before they are shipped to the customers. Contact resistance variability can create inaccurate test results, false failures, increase test time and yield losses. The need for compensating resistance variability will provide accurate test results with improved yield and test time, thus reducing the cost of semiconductor testing. This resistance calibration technique measures the resistance variability in the path from the ATE pogo pins to the device pins, which also includes contact resistance of the probe needles, by forming a Kelvin Connection using the device’s internal DFT, eliminating the need for special design requirements. The method has proven to improve yield by 1.25% tested on a 12-inch wafer with 12638 devices.
As the industry advances towards smaller geometries for integrated circuits (ICs), internal cell defects have become increasingly crucial to address. Cell-Aware Testing (CAT) has emerged as the industry standard for achieving the high-quality levels required in modern ICs, as it explicitly targets intra-cell defects. However, the comprehensive defect coverage provided by CAT can result in a high test pattern count, which directly impacts test time and production costs.This paper proposes two complementary methodologies to optimize the cell library characterization phase by leveraging weak detections to maximize the number of Don’t Cares (DCs) and equivalent defects. The proposal produces an optimized Defect Detection Matrix (DDM) for the library, which is then used by the ATPG for pattern generation at the design level.The methodologies have been validated by running CAT ATPG for five different designs, using a 65nm cell library characterized with the proposed approach. The experimental results show that using the optimized DDMs reduces the number of patterns by an average of 8% and the pattern generation time by 11%, depending on the methodology used and the circuit analyzed.
A new test compression scheme is proposed by using a new DFT architecture, a new gating technique, and a new low-power test application scheme for circuits with a large number of unknown test response sources. A probabilistic measure is proposed to analyze the potential of scan flip-flops to capture unknown responses. All scan flip-flops with enough potential to capture unknown test responses are clustered to localize the effect of the unknown sources on fault coverage. A new test response compactor is presented to avoid unknown test responses and minimize fault coverage loss in the software-defined linear feedback shift-register (SLFSR) based test compression environment. Experimental results are presented to show the effectiveness of the new method.
Trimming is a critical step in ensuring the performance uniformity of integrated circuits (ICs), typically achieved by adjusting control variables to align target specifications. However, in practical scenarios, the relationship between control variables and performance metrics often exhibits nonlinearity, posing challenges for traditional trimming methods in balancing accuracy and efficiency. To address this issue, this paper proposes a fast nonlinear trimming method driven by performance deviation. The proposed approach learns the mapping between performance deviation and control variables, enabling efficient inverse inference without relying on exhaustive search or iterative back-substitution. Experimental results demonstrate that our method reduces the average number of iterations by 43.3% and achieves a 77.6% success rate in meeting target specifications on the first attempt. These findings highlight the method’s advantages in accuracy, efficiency, and feasibility under complex nonlinear trimming scenarios, as well as its potential for generalization and practical deployment.
TSV fabrication in 3D ICs remains immature, causing resistive open-circuit and leakage faults. Pre-bond testing of TSVs improves 3D IC yield and performance. This paper proposes a fully digital pre-bond TSV delay-fault detection scheme using a dual-stage DCDL and a Bang-Bang Phase Detector, a delayed resolution of about 1.52 ps was achieved. 45 nm CMOS HSPICE simulations verify detection of R-open >= 0.2 k Omega and R-leak <= 3.3 M Omega, significantly enhancing accuracy.
In this work, we propose a speed margining scheme to mitigate silent data corruption in a multi-core system. At the hardware level, we incorporate an enhanced architecture based on dual module redundancy (Enhanced DMR), in which each computing core has two gears: standard performance gear (Standard Gear) and shadow performance gear (Shadow Gear). Such an arrangement allows us to establish a safe performance margin with an SDC-alerting capability. At the system level, we demonstrate the benefits of this method on the ZYNQT-7010 FPGA platform. We used seven sets of representative learning programs to emulate various workload conditions. Experimental results show that our system can mitigate the SDC risk by establishing a safe performance margin.
Effect-Cause diagnosis procedures are used to diagnose failing dies and improve manufacturing yield. Several methods have been proposed to accelerate Effect-Cause diagnosis procedures by utilizing a small-sized fault signature dictionary. Recently, pre-silicon diagnosis simulation has been proposed to identify quality issues in diagnosis before silicon volume production. Asymmetric Partition Trees (APT) have been proposed to extract useful information in the fault dictionary for diagnosis simulation applications. APT has proven to have a minimum tree size. In this paper, we propose using fault group information in APT to distribute the fault signature dictionary across APT tree nodes. With APT, the small fault signature dictionary can be further reduced, thereby improving diagnosis performance. The larger the designs, the greater the savings.
This paper proposes a millimeter-wave frontend circuit with highly accurate power levels for automated test equipment application. For the precise testing of numerous radio frequency (RF) signals, the frontend circuit includes a compact gamma measurement circuit to integrate many RF channels into a limited area, and a waveguide RF port to minimize undesired reflections for ensuring high accuracy power levels. Experimental results with a prototype frontend circuit demonstrate the effectiveness of the proposed method.
Accurate wafer defect detection is critical for yield control in advanced semiconductor manufacturing. Traditional rule-based and CNN-based methods struggle with subtle, low-contrast anomalies, while transformer detectors often suffer from high computational overhead. We propose FALCO-WAFER, a lightweight, feature-aware detector tailored for region-of-interest patches from inline AOI systems. Our architecture combines a Multi-Scale Depthwise Block for efficient texture encoding with a Token-Energy Diagonal Attention head for robust feature refinement, enabling anchor-free inference at arbitrary resolutions. Evaluated on a real-world dataset with 5,723 labeled defect images, FALCO-WAFER achieves 90.7% AP@0.5 and 7.19% FNR using only 13.3M parameters, outperforming both CNN and transformer baselines. Its compact design supports low-latency deployment in high-throughput inspection lines. Code is available at: https://github.com/MrJoker06/FALCO-WAFER.
Hyper-dimensional computing (HDC), a brain-inspired architecture, is gaining attention for edge AI due to its noise resilience and suitability for resource-constrained environments. However, its deployment in safety-critical domains exposes HDC to critical security vulnerabilities, including data poisoning and intellectual property (IP) theft. We demonstrate a practical side-channel attack on an FPGA-based binary HDC accelerator using voltage fluctuations captured by Time-to-Digital Converters (TDC) sensors to extract its IP, such as class hypervectors. By introducing collision analysis combined with an implicit triggering mechanism, we achieve a maximum of approximate to 83% bit recovery of a single class hypervector using a few hundred traces, even under parallel operations. We also discuss a randomization countermeasure that effectively reduces the recovery accuracy to approximate to 19% without sacrificing classification performance.
In recent years, approximate computing has been widely adopted in error-tolerant applications. For approximate multipliers, several techniques have been proposed that truncate lower bits based on the magnitude of the operands. In testing approximate circuits, excluding acceptable faults that affect only within the allowable error range can reduce test costs. This paper proposes a test pattern generation method for approximate multipliers based on the Enhanced Static Segment Method. In the proposed method, a constraint circuit used only during the test pattern generation phase is designed to identify acceptable faults, which reside in the truncated region and do not affect the final computation result. Since some faults cannot be detected without detecting acceptable faults, the proposed method also inserts test points to detect such faults under the condition that acceptable faults remain undetected. As a result, the proposed method achieves approximately 32.7% reduction in the number of test patterns, demonstrating its effectiveness in improving test efficiency for approximate arithmetic circuits.
Systolic-array AI accelerators operating near threshold voltage face significant timing reliability challenges due to increased PVT sensitivity. While Razor flip-flops offer accurate bit-level detection, their area overhead limits scalability. Existing timing monitors are more efficient but lack granularity and adaptability. This work presents a frontier-aligned timing monitor that enables low-overhead, bit-level visibility. By analyzing post-layout delays in a 7nm systolic array, we identify a MAC unit highly correlated with the global bit-wise delay frontier. A co-located monitor path with tunable delay buffers enables PVT-aware calibration and precise alignment. Experimental results show an average delay error of 3.1% and area overhead as low as 0.1% in large arrays. The proposed design supports scalable, energy-efficient runtime approximation and adaptive voltage/frequency scaling (AVFS), offering a practical solution for fine-grained timing management in modern AI accelerators.
Battery management system (BMS) is a key component to keep battery packs operating in safe and enduring conditions. This paper presents a SystemC-AMS-based BMS simulation platform including both BMS control and cell modeling designed to support fault injection and modular protection analysis. Through single-bit fault injection experiments, only a small fraction (12.8%) of injected faults violate the safety conditions. And SOC estimation and ADC modules are identified as the most critical components with faults covering all severe conditions such as overcharge, overdischarge and overheating. After applying dual module redundancy (DMR), we can enhance the reliability and reduce safety violations from the original 92321 errors to 72020 and 7860 errors or 78.01% and 8.51%, respectively for ADC and SOC modules. With DMR protection for both the ADC and SOC modules, we can eliminate all safety violations.
Randomized benchmarking (RB) is widely used in the calibration process of quantum computers with the main focus on average gate fidelity. This work proposes a version with the ability of detecting user-specified faults, and successfully detected faults in simulations and real IBM quantum processors. Our proposal can evaluate error per gate (EPG) and detect faults at the same time. We have shown our FDRB successfully detect axial-tilt fault and rotation fault in both simulation and real experiments. The overhead of our proposal is the quantum native gate count increase depending on the number of faults specified by the user.
For any unambiguous transfer of information it is critical to provide a comprehensive description of components, operations, procedures, methodology etc. defined by a technical standard. Many standards provide a descriptive language to capture and transfer information. In this paper we present a descriptive language model for Die-to-Die (D2D) interconnect test and repair, which is under development in the framework of IEEE P3405 standard. We show its capability to describe interconnect, repair scheme, and its application to existing interconnect standards like UCIe, AIB and HBM. We report the impact of various design parameters in a repair IP on the algorithm’s runtime, which extracts the repair algorithm and generates valid repair solutions from the given descriptive language in JSON format.
Digital Signal Processor (DSP) systems frequently manage highly sensitive data within critical sectors such as telecommunications, healthcare, and defense. However, DSP are vulnerable to attacks such as unauthorized access, reverse engineering and software vulnerabilities. To enhance the security of sensitive data without significantly increasing DSP hardware overhead, we propose ELSeM, an efficient and lightweight security mechanism specifically tailored for DSP. It utilizes Direct Memory Access(DMA) in conjunction with electronic fuse(efuse) and SM4 modules to encrypt/decrypt key data through data transmission process and obtain security permissions after successful key comparison. ELSeM offers several advantages: 1) Enables efficient encryption and decryption of data with variable pipeline stages of SM4 during DMA transfer process; 2) Lightweight, consumes minimal resources, which is specifically tailored for DSP; 3) Restrict arbitrary key access and employ redundancy backup which mitigates unauthorized chip access, thereby significantly enhancing chip security. We implement the ELSeM with RTL and conduct tape-out, verifying its security at chip level. The experimental results indicate that the hardware overhead of ELSeM is minimal, approximately 0.1%, and the activation or deactivation of SM4 functionality has virtually no effect on DMA throughout.
