A compact silicon photonics multi-wavelength filter is demonstrated using superimposed sidewall Bragg gratings. We show arbitrary wavelength spacing with 8 superimposed gratings on a total footprint that is equivalent to a single Bragg grating device. Integrated waveguide Bragg gratings are one of the fundamental building blocks in the Photonic Integrated Circuit (PIC) designer’s toolkit. The concept of using the bandgap region of an inline grating device as a spectral filter is well established and has been used across material platforms for laser design [1], dispersion engineering [2] and sensing applications [3]. In the silicon-oninsulator (SOI) platform the high optical confinement of the mode to the grating area allows unprecedented control over the grating coupling coefficient and Bragg wavelength, producing a wide variety of filter designs in both amplitude and phase domains [4,5]. Furthermore the sinusoidal sidewall variation commonly employed to create the periodic grating function is easily implemented in standard nanofabrication lines and can be controllably engineered. Fig. 1: Schematic of a superposition grating with two separate grating periods. SEM images show the amplitude variation of the sidewall grating along the device length due to beating between the two grating periods. The devices presented here are made by superimposing up to 8 grating periods over a total device length of 200 μm. The simplest approach to achieving multiple filter bands in a single waveguide is by cascading individual gratings with variable Bragg wavelengths. This geometry, however, produces grating lengths of at least NxLg, where N is the number of required filter bands and Lg is the individual grating length. In this work we demonstrate an alternative superstructured Bragg grating device that exhibits multiple filter bands with arbitrary wavelength spacings and with a footprint equivalent to a single Bragg grating device. The superstructured grating design is similar in concept to the multi-exposure technique used in fibre grating designs. Single sidewall perturbation functions An(z) can be defined as simple sinusoidal variations that produce the usual Bragg grating response, where An(z)=ansin(2πz/Λn), and Λn is the Bragg grating period for the n th filter response. The summation of these individual sidewall perturbation functions, ∑ , produces a total sidewall perturbation function with N Fourier components that will create N grating responses within the same physical length as a classical single period grating. In addition, the extinction of the filters can be weighted using their individual perturbation amplitudes an. The device geometry is illustrated by the schematic of Fig.1 that shows the profile of the sidewall grating when two separate grating periods are superimposed. In this work several grating devices based on an 8-wavelength basis set were fabricated and characterised. Arbitrary combinations of these 8 basis functions were shown to match simulated results and underline the equivalence of this device to a cascade of individual filters. Fig. 2: Measured (blue curve) and simulated (red dotted curve) grating transmission spectra for two different superposition grating devices. The binary numbers indicate the gratings of the 8-basis wavelength set that were ‘on’ for each device. The results of Fig. 2 indicate that any arbitrary combination of filter wavelengths can be fabricated in a single superposition with excellent agreement to the designed transfer function. Furthermore, the total length of the grating device is only 200μm, which is far more compact than the equivalent serial grating geometry. In conclusion we have demonstrated a compact means by which to generate a multiwavelength filter with non-repetitive filter band positions. Up to 8 grating filter bands are demonstrated in 200μm long devices on a single silicon waveguide. This same approach can be easily extended to the design of more complex transfer functions with arbitrary filter wavelengths that exhibit different reflectivities, bandwidth and phase profiles.

Frequency (100 Hz ≤ f ≤ 1 MHz) and temperature (-50 ≤ T 20 °C) characteristics of low interface state density D it high-κ gate-stacks on n-InAs have been investigated. Capacitance-voltage (C-V) curves exhibit typical accumulation/depletion/inversion behavior with midgap D it of 2 × 10 11 and 4 × 10 11 cm -2 eV -1 at -50 °C and 20 °C, respectively. Asymmetry of low-frequency C-V curves and C-T dependence for negative voltage showing a sharp transition of ≅-20 dB/decade between low- and high-frequency behavior indicate surface inversion. An inversion carrier activation energy and an InAs hole lifetime of 0.32 eV and 2 ns have been extracted, respectively. Surface channel nMOSFETs with gate length L g = 1 μm, channel thickness = 10 nm, and equivalent oxide thickness (EOT) 1 ≤ EOT ≤ 1.6 nm have been fabricated. For EOT = 1 nm, a subthreshold swing S = 65 mV/decade, transconductance g m = 1.6 mS/μm, and ON-current I ON = 426 μA/μm at an OFF-current I OFF = 100 nA/μm (supply voltage V dd = 0.5 V) have been measured. Peak electron field-effect mobilities of 6000-7000 cm 2 /Vs at sheet electron densities of 2-3 × 10 12 cm -2 were obtained for EOT as small as 1 nm.

Multiple-filter stopbands, with the potential to be nonuniformly spaced in frequency, are realized in a single integrated Bragg grating device on silicon. By utilizing a superposition of sidewall relief grating functions, N individual filter responses can be fabricated with a device length N× shorter than the equivalent serial set of gratings. Arbitrary combinations of eight-basis filter responses were demonstrated as selected by an eight-bit pseudorandom number generator, showing the flexibility of the complex Bragg grating device design.

The authors describe a modification to the alignment algorithm typically used for electron beam lithography. Extra markers are used, which increases accuracy, but more importantly enables misplaced markers to be detected and discounted. This has the advantage of eliminating the effect of occasional poor markers and also gives a measure of the expected alignment accuracy after marker search and prior to writing. Two methods for identifying outliers are discussed, the first being a conventional least squares approach in which outliers are rejected one by one. The second approach uses the method of trimmed least squares, which is a more robust regression method, and was found to give better results. With 16 or more evenly distributed markers around the edge of the pattern both methods were found to give good results. Both modeled and experimental data were used to evaluate the use of additional markers. The experimental results showed that with 24 markers, 10 of which had position errors between 100 and 300 nm, a final alignment accuracy of 20 nm could be obtained. Finally this technique can be used to identify rogue markers, which is an important first step toward rectifying the process issues which led to the formation of poor markers in the first place. This is particularly important during process development, which is a major part of the typical throughput of an electron beam lithography tool.

This paper reports a simple route to fabricating T-gate like structures with footprint of 40nm using a copper electroplating process and a single electron beam lithography step without the need for lift-off. To our knowledge, these are the smallest such structures demonstrated using this approach which could also be implemented straightforwardly using conventional stepper or nanoimprint lithography for low cost, high volume silicon compatible manufacture.

Silicon nanowires have been patterned with mean widths down to 4 nm using top-down lithography and dry etching. Performance-limiting scattering processes have been measured directly which provide new insight into the electronic conduction mechanisms within the nanowires. Results demonstrate a transition from 3-dimensional (3D) to 2D and then 1D as the nanowire mean widths are reduced from 12 to 4 nm. The importance of high quality surface passivation is demonstrated by a lack of significant donor deactivation, resulting in neutral impurity scattering ultimately limiting the electronic performance. The results indicate the important parameters requiring optimization when fabricating nanowires with atomic dimensions.

CSAR 62 is a new positive tone electron beam resist designed to have similar performance to ZEP520A in resolution, speed, and etch resistance. In this paper, the authors have used the resist to carry out high resolution electron beam lithography and as a mask for reactive ion etching on dielectrics, gallium arsenide, and silicon substrates coated with a 160 nm film of aluminum. Comparisons have been made between the results obtained using CSAR 62, ZEP520A, and polymethylmethacrylate. The authors conclude that CSAR 62 does demonstrate similar resolution, sensitivity, and etch resistance as ZEP520A but also gives rise to substantial resist residuals after development. These are almost entirely eliminated by using an alternative developer.

A compact silicon photonics multi-wavelength filter is demonstrated using superimposed sidewall Bragg gratings. We show arbitrary wavelength spacing with 8 superimposed gratings on a total footprint that is equivalent to a single Bragg grating device.

Planar devices that can be categorised as having a nanophotonic dimension constitute an increasingly important area of photonics research. Device structures that come under the headings of photonic crystals, photonic wires and metamaterials are all of interest - and devices based on combinations of these conceptual approaches may also play an important role. Planar micro-/nano-photonic devices seem likely to be exploited across a wide spectrum of applications in optoelectronics and photonics. This spectrum includes the domains of display devices, biomedical sensing and sensing more generally, advanced fibre-optical communications systems - and even communications down to the local area network (LAN) level. This article will review both device concepts and the applications possibilities of the various different devices.

Deep submicron gaps between metal pads of around 100 μm in size are difficult to fabricate on III-V substrates using electron beam lithography, polymethyl methacrylate (PMMA) resist, and metal lift-off. In device fabrication, gold is commonly used to form metal contacts. However, gold etch methods are not well suited to high resolution patterning and lift-off methods are frequently employed. In this paper, the authors investigate a number of different methods for realizing long 100 nm scale gaps for structures fabricated on III–V substrates. Initially, they explain why the fabrication of long narrow gaps between metal pads using PMMA resist and metal lift-off is difficult. The authors show that 15 nm gaps can be fabricated using a double patterning method and discuss the limitations of this technique. They show that good undercut profiles for metal lift-off can be realized by the controlled etching of a sacrificial polymer layer placed beneath the resist. The authors demonstrate that reliable 100 nm scale gaps can be fabricated between 100 μm square metal pads using these methods.

In this letter, we investigate the scaling potential of flatband III-V MOSFETs by comparing the mobility of surface and buried-channel In0.53Ga0.47As devices employing an atomic layer-deposited Al2O3 gate dielectric and a delta-doped InGaAs/InAlAs/InP heterostructure. Peak electron mobilities of 4300 cm2/V · s and 6600 cm2/V · s at a carrier density of 3 × 1012 cm-2 were determined for the surface...

Experimentally measured optical properties of photonic crystal LEDs are reported here. Photonic crystal and photonic quasi-crystal structures were fabricated on GaN epilayer LED wafer material using both direct-write electron beam lithography and nanoimprint lithography. Some of these structures were processed to make finished LEDs. Both electroluminescence and photoluminescence measurements were performed on these structures. Devices were characterized for their current-voltage characteristics, emission spectra, far-field emission pattern, and angular emission pattern. These results are useful for fabricating photonic crystal LEDs and assessing their operational properties.

The high electron mobility of compound semiconductor materials, arising from the combination of low effective mass and materials dependent intervalley scattering mechanisms, can result in high velocity and low backscatter electrons being injected at the source side of a III–V nMOSFET. In combination, these factors have the potential to meet the highly challenging performance metrics of the International Technology Roadmap for Semiconductors (ITRS) [1] beyond the 15nm technology generation, in particular the need to reduce supply voltages towards 0.5V. This paper highlights some challenges over and above those of developing a high quality dielectric/III–V semiconductor interface, specifically in the areas of scaled source/drain contact formation and channel materials and device architectures which have to be addressed if III–V MOSFETs are to be a credible solution to enable continued scaling of the ITRS beyond 2018.

In this letter, we investigate the scaling potential of flatband III-V MOSFETs by comparing the mobility of surface- and buried-channel In0.53Ga0.47 As devices employing an atomic-layer-deposited Al2O3 gate dielectric and a delta-doped InGaAs/InAlAs/InP heterostructure. Peak electron mobilities of 4300 cm(2)/V . s and 6600 cm(2)/V . s at a carrier density of 3 x 10(12) cm(-2) were determined for the surface-and buried-channel structures, respectively. In contrast to similarly scaled inversion-channel devices, we find that the mobility in surface-channel flatband structures does not drop rapidly with the electron density, but rather high mobility is maintained up to carrier concentrations around 4 x 10(12) cm(-2) before slowly dropping to around 2000 cm(2)/V . s at 1 x 10(13) cm(-2). We believe these to be world leading metrics for this material system and an important development in informing the III-V MOSFET device architecture selection process for the future low-power highly scaled CMOS.

In this paper we discuss theoretical modelling methods for the design of photonic crystal and photonic quasi-crystal (PQC) LEDs - and apply them to the analysis of the extraction enhancement performance and shaping of the emitted beam profile of PQC-LED structures. In particular we investigate the effect of the pitch of the PQC patterning, and consider the physical mechanisms giving rise to performance improvements. In addition, we examine the relative contributions to performance improvements from effective index reduction effects that alter the conditions for total internal reflection at the device air interface, and from photonic crystal scattering effects that give rise to radically improved extraction performance. Comparisons are made with the performance of recently fabricated devices.

Kelvin probe force microscopy (KPFM) is a unique technique that can provide two-dimensional potential profiles inside a working device. A procedure is described to obtain high-resolution KPFM results on ultra-high vacuum (UHV) cleaved III-V MOSCAPs. Two tip preparation methods: field emission and Cr coating show reproducible high spatial and energy resolution KPFM images. A unique sample design has been developed which is compatible with UHV cross-sectional KPFM (x-KPFM). Key design features are high density of devices on the cleave face, a buried device interface, and a cleavable gate contact. Using x-KPFM, the first UHV cleaved MOSCAP surface potential mapping is demonstrated.

We describe a comparison of nanofabrication technologies for the fabrication of 2D photonic crystal structures on GaN/InGaN blue LEDs. Such devices exhibit enhanced brightness and the possibility of controlling the angular emission profile of emitted light. This paper describes three nano lithography techniques for patterning photonic crystal structures on the emitting faces of LEDs: direct-write electron beam lithography, hard stamp nanoimprint lithography and soft-stamp nanoimprint lithography with disposable embossing masters. In each case we describe variations on the technique as well as its advantages and disadvantages. Complete process details have been given for all three techniques. In addition, we show how high performance GaN dry etch techniques, coupled with optical process monitoring can transfer resist patterns into underlying GaN material with high fidelity.

The fabrication of 2-dimensional (2D) photonic quasi crystals (PQCs) on gallium nitride (GaN) light emitting diodes (LEDs) is described. Fabrication was achieved using electron beam lithography (EBL) and, separately, by nano-imprint lithography (NIL).

This article describes a process flow that has enabled the first demonstration of functional, fully self-aligned 100nm enhancement mode GaAs metal-oxide-semiconductor field-effect transistors (MOSFETs) with GaxGdyOz as high-κ dielectric, Pt∕W as metal gate stack, and SiN as sidewall spacers. The flow uses blanket metal and dielectric deposition and low damage dry etch modules. As a consequence, no critical dimension lift-off processes are required. Encouraging data are presented for 100nm gate length devices including threshold voltage of 0.32V, making these the shortest, fully self-aligned gate length enhancement mode III-V MOSFETs reported to date. This work is a significant step forward to the demonstration of high performance “siliconlike” III-V MOSFETs.