Stacking devices in a 3D configuration by using a vertical topology is considered as the next step to improve electronic devices and circuits performance. For instance, a CMOS inverted can be built by continuously depositing both inter-metal and metal layers. This new IC manufacturing proposal has been simulated by using Sentaurus 3D TCAD software. We have analyzed the influence of different device design parameters to optimize its performance. Finally, we have also explored the feasibility to implement a 5-stage ring oscillator circuit by using the proposed stack.

This study addresses the complementary metal-oxide-semiconductor-compatible fabrication of vertically stacked Si/SiO 2 /Si nanopillars (NPs) with embedded Si nanodots (NDs) as key functional elements of a quantum-dot-based, gate-all-around single-electron transistor (SET) operating at room temperature. The main geometrical parameters of the NPs and NDs were deduced from SET device simulations using the nextnano++ program package. The basic concept for single silicon ND formation within a confined oxide volume was deduced from Monte-Carlo simulations of ion-beam mixing and SiO x phase separation. A process flow was developed and experimentally implemented by combining bottom-up (Si ND self-assembly) and top-down (ion-beam mixing, electron-beam lithography, reactive ion etching) technologies, fully satisfying process requirements of future 3D device architectures. The theoretically predicted self-assembly of a single Si ND via phase separation within a confined SiO x disc of <500 nm 3 volume was experimentally validated. This work describes in detail the optimization of conditions required for NP/ND formation, such as the oxide thickness, energy and fluence of ion-beam mixing, thermal budget for phase separation and parameters of reactive ion beam etching. Low-temperature plasma oxidation was used to further reduce NP diameter and for gate oxide fabrication whilst preserving the pre-existing NDs. The influence of critical dimension variability on the SET functionality and options to reduce such deviations are discussed. We finally demonstrate the reliable formation of Si quantum dots with diameters of less than 3 nm in the oxide layer of a stacked Si/SiO 2 /Si NP of 10 nm diameter, with tunnelling distances of about 1 nm between the Si ND and the neighboured Si regions forming drain and source of the SET.

Random Telegraph Noise (RTN) and Bias Temperature Instabilities (BTI) are two mechanisms that can significantly reduce the performance and reliability of integrated circuits. In scaled devices, both phenomena are stochastic, so that a statistical analysis is required to accurately evaluate their impact on a particular technology. This study presents such analysis in scaled FD-SOI devices under various gate and drain voltages, ranging from near-threshold to nominal conditions. The combined effect of RTN and BTI is also modeled in a defect-centric context, and the main impact of the different bias conditions is discussed.

Stacking devices in a 3D configuration by using a vertical topology are the next step to reduce electronic devices and circuits area foot-print. We propose the realization of a CMOS inverter by multiple sequential deposition of inter-metal and metal layers around a vertical NW. This new device concept is simulated and optimized by using Sentaurus 3D TCAD simulations. We prove the suitability of this proposal and analyze the influence of different device design parameters to enhance its performance.

This study analyzes feasibility of complementary metal–oxide–semiconductor (CMOS)-compatible manufacturing of a hybrid single electron transistor–field effect transistor (SET-FET) circuit. The fundamental element towards an operating SET at room temperature is a vertical nanopillar (NP) with embedded Si nanodot generated by ion-beam irradiation. The integration process from NPs to contacted SETs is validated by structural characterization. Then, the monolithic fabrication of planar FETs integrated with vertical SETs is presented, and its compatibility with standard CMOS technology is demonstrated. The work includes process optimization, pillar integrity validation, electrical characterization and simulations taking into account parasitic effects. The FET fabrication process is adapted to meet the requirements of the pre-fabricated NPs. Overall, this work establishes the groundwork for the realization of a hybrid SET-FET circuit operating at room temperature.

We investigate the benefits of the use of arrays of vertical nanowire (vNW) field-effect transistors (FETs) to implement integrated circuits. By means of technology computer aided design and circuit simulations, the optimal dimensions of the vNWFETs are determined. Device and circuit variability levels have been investigated. The benefits of using array configurations are the decrease of the response time and a significant mitigation of the variability level as the number of the elements in the array increases.

Carry out an electronic device/circuit at the scale of few nanometers usually implies a high level of uncertainty due to device variability along the fabrication process. In fact, hybrid SET-FET circuit can be extremely delicate in front of parasitic elements, due to the low level of current provided by the SET device. So, in this contribution and study of their influence is done. Moreover, the suitability to implement this circuit by using FinFET SOI is observed, as well.

This contribution explores different strategies to electrically contact vertical pillars with diameters less than 100 nm. Two process strategies have been defined, the first based on Atomic Force Microscope (AFM) indentation and the second based on planarization and reactive ion etching (RIE). We have demonstrated that both proposals provide suitable contacts. The results help to conclude that the most feasible strategy to be implementable is the one using planarization and reactive ion etching since it is more suitable for parallel and/or high-volume manufacturing processing.

Quantum dots (QDs) can be used as conductive islands to build-up single-electron transistors (SETs). The characteristics of the QDs define the functional performance of the SETs. In consequence, analyzing the influence of the variations of QD dimensions on the performance of hybrid SET-FET circuits is of high relevance. We employ a self-developed SET compact model which is calibrated to 3-D quantum-mechanics-based simulations in order to obtain realistic model parameters. A method to improve the circuit behavior, i.e., to increase the output current, is proposed. It is concluded that the variation of the QD size presents the largest influence on the overall circuit behavior.

Sub-threshold circuits (sub-V-T) are a promising alternative in the implementation of low power electronics. The implementation of gain-cell embedded DRAMs (eDRAMs) based on FinFET devices requires a careful design to achieve the maximum cell performance (i.e., retention time, access time, and energy consumption) suitable for the sub-V-T operating level. In this work, we show that asymmetrically resizing the memory cell (i.e., the channel length of the write access transistor and the width of the rest of the devices) results in a 3.5x increase in retention time when compared to the nominal case while reducing area, as well. In terms of reliability (e.g., variability and soft errors), the resizing also improves the cell robustness (50% and 1.9x, respectively) when the cells are operated at sub-V-T level.

With the advent of the slowdown in DRAM capacitor scaling [1] and the increased reliability problems of traditional 6T SRAM memories [2], industry and academia have looked for alternative memory cells. Among those, gaincells have attracted significant attention due to their smaller size (compared to SRAM) and non-destructive read operation (compared to DRAM) as well as considerable low power and reasonable robustness. This paper first summarizes the available evidences of SRAM and eDRAM in commercial and test chips. Then, it analyzes the performance, reliability and scaling of eDRAM gain-cells in 10 and 7 nm FinFET technology; as well as above and below VT (i.e. sub-threshold).

Hybrid SET-FET circuits are candidates to extend the SET usefulness for low power circuits and with high integration density. The location of quantum dot (QD) of the SET is usually expected at the centre of the tunneling barrier, but out this ideality the QD may not be precisely located. For this, to analyse the impact of the QD location variation will be of high interest to predict the hybrid circuit behaviour.

We summarize most of our studies focused on the main reliability issues that can threat the gain-cells eDRAM behavior when it is simulated at the nano-metric device range has been collected in this review. So, to outperform their memory cell counterparts, we explored different technological proposals and operational regimes where it can be located. The best memory cell performance is observed for the 3T1D-eDRAM cell when it is based on FinFET devices. Both device variability and SEU appear as key reliability issues for memory cells at sub-22nm technology node.

We investigate the fabrication of sub-20 nm pillars by DSA lithography using PS-cylinder-forming PS-b-PMMA block copolymer (BCP). The approach is based on the removal of PMMA-matrix by either dry or wet etching to form PS pillars which act as a soft etching mask that can be further transferred to an intermediate hard one and then to the substrate. The process conditions of BCP self-assembly were optimized in terms of annealing temperature, brush layer composition and film thickness. It was demonstrated that PS/PMMA volume fractions of 50/50 in the PS-r-PMMA brush layer is the most adapted to obtain standing PS cylinders. Top-down SEM images showed a hexagonal array of PS cylinders in a PMMA matrix with a natural period of 33.5 nm (determined by Fast Fourier Transform FFT method) and CD around 15 nm. Both wet and dry etching strategies for PMMA removal were discussed. It was shown that UV exposure followed by organic solvent development is necessary to decrease pattern collapsing during PMMA removal step which is the most critical issue for pillar fabrication. PMMA removal by dry etching was shown to completely avoid this pattern collapsing. Finally, pillars etching transfer to typical organic Si containing antireflective coating and spin on carbon (SiARC/SOC) hard mask and then to the silicon substrate was demonstrated. Si pillars of 15 nm CD and 70 nm height were obtained with a straight profile shape.

In this work, an electrical study of a vertical nanowire (NW)-based Field Effect Transistor (FET) is presented. The resulting output current from the modelled NW-FET is optimized in terms of multiple parameters, in order to enhance the behavior at subthreshold regime. Variability tolerance is analyzed as well, in order to attain improvements concerning average device performance and stability. A process simulation model for a NW-FET is built in perspective for its further manufacturability and implementation into hybrid SET-FET circuits.

We analyze the performance of hybrid single-electron transistor (SET)-FET circuits when different variability sources are considered, e.g., SET's quantum dot location and FET device dimension variations. For the FET device, FinFET and vertical nanowire configurations have been studied. The hybrid SET-FET circuits with both SET and FET in vertical topology depict the best circuit performance and the highest integration level. The variability impact on different SET-based circuits has been analyzed, including negative differential resistance and logic inverters.

The scaling roadmap for realization of more than Moore in semiconductor industry has resulted in emergence of new types of devices, among them, memristive devices seem to be a promising candidate to be applied in various applications such as in memories and neuromorphic chips. However memristive devices face some challenges to be resolved before becoming a mainstream. This paper work analyzes two of the main reliability concerns in design of memristive memories, and proposes circuit solution to enhance the reliability. Keywords—Memritor; reliability; process variability; endurance; crossbar; RRAM; reconfiguration; emerging device.

Bio-medical wearable devices restricted to their small-capacity embedded-battery require energy-efficiency of the highest order. However, minimum-energy point (MEP) at sub-threshold voltages is unattainable with SRAM memory, which fails to hold below 0.3V because of its vanishing noise margins. This paper examines minimum-energy operation of 2T and 3T1D e-DRAM gain cells as an alternative to SRAM at 32nm technology node with different design points: up-sizing transistors, using high-Vth transistors, read/write wordline assists and temperature. First, the e-DRAM cells are evaluated without considering any process variations. The design-space is explored by creating a kriging meta-model to reduce the number of simulations. Finally, a full-factorial statistical analysis of e-DRAM cells is performed in presence of threshold voltage variations. The effect on mean MEP is also reported.

This paper explores the feasibility, in terms of performance and reliability, of gain-cell embedded DRAM (eDRAM) to be operative at sub-threshold range, when they are implemented with 10nm FinFET devices. The use of individual transistor resizing in order to achieve better cell performance (i.e. retention time, access time, and energy consumption) at the sub-VT operating level is studied. In this scenario, asymmetrically resizing the memory cell, since we modify the channel length of the write access transistor and the width of the rest of the devices in the eDRAM cell, entails a 3.5x increase in retention time as compared to the nominal case and with smaller area overhead. Moreover, such a resizing significantly improves reliability against variability and soft errors (50% and 1.9x, respectively) when the cells are operated at sub-VT level.