Two-dimensional semiconductors are promising channel materials for continuing transistor scaling and extending Moore's law. However, as transistor density increases, the area available for contacts shrinks, making low-resistance contacts a critical challenge. Here, we theoretically investigate the performance and scalability of edge, top, and hybrid contacts to MoS2 monolayers. Using a quantum transport model that includes key mechanisms such as image-force barrier lowering as well as open vertical metal leads, we compare the contact resistance of these geometries while analyzing the impact of parameters such as doping concentration, surrounding dielectrics, metal work functions, van der Waals gap thickness, and contact length. We find that hybrid contacts generally yield the best performance, especially when scaled to contact lengths below 10 nm, achieving a contact resistance close to the quantum limit at doping concentrations above 1013 cm-2. The edge contact exhibits the poorest performance under most circumstances, as it suffers from higher Schottky barriers and lacks mechanisms to reduce them. While the top contact performs well, the hybrid contact shows significantly lower resistances at extreme scaling because it is less sensitive to long transfer lengths.

We study theoretically electron transport in an top-and bottom-gated (100) 1.6 nm-thin silicon nanosheet with SiO2/HfO2 gate stacks, focusing on the intrinsic physical processes that affect transport: the confinement of phonons and the presence of interface hybrid plasmon-phonon excitations (IPPs or `remote phonons'). The band structure is calculated using local empirical pseudopotentials; an approximated elastic continuum model is used to consider the confinement of acoustic phonons; the dielectric continuum limit is used to deal with the IPPs. We find that the electron mobility is affected significantly by the boundary conditions chosen to deal with phonon confinement. The more realistic assumption of phonons clamped at the SiO2/HfO2 interfaces and optical phonons at the Si/SiO2 interfaces results in a room temperature mobility much smaller than what is obtained using the common assumption of bulk phonons in the elastic, high-temperature approximation. We also find that, as a result of the complicated structure of the primed subbands, the high-field saturated velocity is significantly lower than its bulk value, as it had been measured in the past in the case of Si inversion layers but never explained theoretically. Finally, we find that IPP scattering does depress the low-field mobility but to a small extent, thanks to the presence of the interfacial SiO2 layers and to the proximity of the metal gates. Moreover, by keeping electrons `cooler', IPP scattering results in a higher saturated velocity. Therefore, the presence of high-kappa materials in the gate-insulator stacks should not affect negatively the performance of field effect transistors based on Si nanosheets.

We argue that the static dielectric constant of small (thin and/or narrow) semiconductor and insulator nanostructures depends strongly on the their environment. We do so by considering the electronic response simply reviewing, briefly but critically, the existing literature. Regarding the ionic response, in addition to reviewing the literature, we use a simple model to account for the confinement of optical phonons in thin films and show that the reduction of their density of states has a negligible effect on the dielectric constant, in contrast to some claims found in the literature. In general, we argue that in realistic structures, such as double-gated Si nanosheets, the use of the bulk dielectric constants for both the channel and the gate insulators, is justified.

The performance of silicon nano-devices at cryogenic temperatures is critical for quantum qubit control circuits and space applications. Using multi-valley Monte Carlo simulations, we investigate electron transport in Si (110) systems. At low electric fields, phonon absorption becomes negligible, and mobility is governed by competition between remote Coulomb scattering (RCS) at low inversion charge density and surface roughness scattering (SRS) at high density, leading to a mobility peak. High-κ dielectrics such as HfO_2 introduce remote phonon scattering (RPS), which suppresses mobility. Under high electric fields, phonon emission dominates at 4 K, limiting velocity enhancement and resulting in limited current improvement

The high demand for data processing necessitates continued transistor scaling in both area and performance. Two-dimensional (2D) materials, such as transition metal dichalcogenides, offer a promising avenue for aggressive scaling, yet significant breakthroughs are still needed for their technological adoption. While substantial progress has been made in improving channel quality, scaling gate dielectrics, and contact pitch miniaturization to the relevant value, challenges in contact, especially in p-type channel and gate integration remain.In this talk, we will explore the current state-of-the-art for 2D material transistors [1], detailing critical challenges focusing on the high access resistance and gate stack. We highlight the need for p-contact engineering schemes beyond those employed in current back-gated devices. Compatibility with nanosheet/gate-all-around architectures is highly desired [2]. Recent advances in device scaling, gate stack scaling, and the required mechanical strength for nanosheets will be discussed.Contact length scaling and increasing ION with channel length scaling down to at least 12nm with low contact resistance are demonstrated, as well as very scaled device length high performance n-type transistor [3], [4]. Optimizing the interfacial layer and surface treatment leads to the ~1.6x mobility enhancement, achieving relevant mobility at a 1.4nm effective oxide thickness [5]. Mechanical strength, a key parameter in nanosheet integration, especially for 2D materials, is enabled by introducing bilayer MoS2. Meanwhile, contact length up to 30nm can be achieved through C-contact geometry. For contact integration, nearly epitaxial metal deposited by ALD shows a work function of ~6.0 eV with WSe2, making it suitable for PMOS. Combined with Phosphorous doping, all elements for fab-compatible contact module are included.We will aim to provide a summary guide of high-value research topics for 2D materials in very scaled transistors.

This study investigates the effect of non-ideal factors in WSe2 2Dmaterial channel transistors, including interface traps $(D_{i t})$, contact resistance $(R_{C})$, and band-tail states $(S_{B T})$, on the threshold voltage $(V_{T})$. For achieving the scaled $V_{D D}=0.75 \mathrm{V}$ operation, reduction of multiple non-idealities is required beyond current state: (i) reducing $D_{i t}$ below 1E12 $\text{cm}^{-2} \text{eV}^{-1}$ preserves the position of $V_{T C C}=-0.1 \mathrm{V}$ (constant-current $V_{T}$); (ii) suppressing the $S_{B T}$ through gate dielectric engineering, with scaled EOT below 1 nm, is required for setting correct $V_{T C C}$ and $V_{T G M}$ (transconductance-defined $V_{T}$) positions; (iii) minimizing $R_{C}$ to $100 \Omega-\mu \mathrm{m}$ ensures the $(V_{T G M}-V_{T C C})$ gap below 0.28 V. The study combines these findings and offers insights to design the desired $V_{T}$ positions at scaled $V_{D D}$ for 2D materials.

We discuss the problem of assessing the electronic and vibrational dimensionality of a semiconductor nanostructure: How thin and/or wide must a nanostructure be in order to induce electron and phonon confinement? Clarifying the physical justification for common criteria found in the literature, we view the electron coherence length (defined as the electron and phonon inelastic mean free path) as their `field of view' and argue (or, better yet, `speculate') that this sets the important length scale. Considering the example of Si nanosheets at room temperature, and drawing from results found in the literature, we estimate that the critical length below which electrons are subject to quantum confinement is of the order of (or smaller than) 8 nm, when their coherence length is determined by energy losses to phonons and remote phonons in gated structures. On the contrary, no single length-scale can be given for phonons: Taking their coherence length as determined by scattering with electrons and anharmonic three-phonon processes, short wavelength acoustic and optical phonons may be confined only by structures as small as 10 nm. Long-wavelength acoustic phonons, instead, may exhibit a coherence length of the order of 1 micrometer, so that they may be confined over much larger distances.

Bilayer transition metal dichalcogenides (TMDs) are promising materials for next-generation field-effect transistors (FETs) due to their atomically thin structure and favorable transport properties. In this study, we employ density functional theory (DFT) to compute the electronic band structures and phonon dispersions of bilayer WS2, WSe2, and MoS2, and the electron-phonon scattering rates using the EPW (electron-phonon Wannier) method. Carrier transport is then investigated within a semiclassical full-band Monte Carlo framework, explicitly including intrinsic electron-phonon scattering, dielectric screening, scattering with hybrid plasmon–phonon interface excitations (IPPs), and scattering with ionized impurities. Freestanding bilayers exhibit the highest mobilities, with hole mobilities reaching 2300 cm2/V·s in WS2 and 1300 cm2/V·s in WSe2. Using hBN as the top gate dielectric preserves or slightly enhances mobility, whereas HfO2 significantly reduces transport due to stronger IPP and remote phonon scattering. Device-level simulations of double-gate FETs indicate that series resistance strongly limits performance, with optimized WSe2 pFETs achieving ON currents of 820 A/m, and a 10% enhancement when hBN replaces HfO2. These results show the direct impact of first-principles electronic structure and scattering physics on device-level transport, underscoring the importance of material properties and the dielectric environment in bilayer TMDs.

Mechanical strength is a key parameter in nanosheet (NS) integration especially for ultra-thin channels such as 2D materials. MoS2 bilayer enables NS channel integrity at longer gate lengths as well as C-contact geometry with an effective contact length (L-eff) of up to 30 nm. To enable contact integration, nearly epitaxial metal is deposited by atomic layer deposition (ALD). The extracted work function is similar to 6.0 eV in contact with WSe2 making it a good candidate for PMOS contact. Combined with Phosphorous doping, all elements for fab-compatible contact module are included here. Just like in 3D semiconductors, channel mobility can be limited by the gate dielectrics. Here we show similar to 1.6x mobility enhancement by introducing an appropriate IL and surface treatment compared to our previous report [1]. The purpose of the IL is to reduce remote phonon scattering from the dielectric while the surface preparation reduces interface defects. Mobility in monolayer WSe2 thus reaches relevant values at a relevant EOT of 1.4 nm.

Efficient digital circuits require CMOS transistors with well-matched threshold voltage $(\mathrm{V}_{\text{TH}})$. In this work, we demonstrate for the first time CMOS co-integration, and well-matched $\mathrm{V}_{\text{TH}}$ showcased through inverters based two-dimensional (2D) materials with supply voltage $(\mathrm{V}_{\text{DD}})$ of 1 V. We compare the fabrication of these circuits using the same channel material with using dedicated $\mathrm{N}$ and $\mathrm{P}$ channel materials (hetero-channel). Both instances use monolayer 2D transition metal dichalcogenide. The hetero-channel inverters allow superior performance at a relevant $\mathrm{V}_{\text{DD}}=1\ \mathrm{V}$: voltage gain exceeding 10 $\mathrm{V}/\mathrm{V}$, noise margin over 80%, low average static-power consumption $\sim 7\ \text{pW}$, and a switching voltage $(\mathrm{V}_{\mathrm{M}})\sim 0.5$ V. While still far from Si performance, reaching these numbers simultaneously requires multiple step developments working well together for monolayer 2D materials in the co-integrated flow. Sensitivity of various electrical metrics to process steps is also discussed in the paper.

We present results on the effect of a surrounding dielectric and a back-gate bias on the resistance of "electrostatically" doped two-dimensional (2D) materials edge-contacts and compare it to contacts to impurity-doped 2D materials. The transmission probability is computed using the Wentzel-Kramers-Brillouin approximation, the full-band density of states obtained from density functional theory, and the potential is obtained from the 2D Poisson's equation. We find that a low-. back-gate oxide with a low-. top dielectric environment results in a lower contact resistance in "electrostatically" doped edge-contacts. The imageforce barrier-lowering is reduced by the back-gate, whereas in impurity doped contacts, it is determined by the dielectric permittivity of the surrounding oxide and of the 2D material. Additionally, we observed that in all cases, "electrostatically" doped devices exhibit worse contact resistance than impurity doped ones, and only very high gate bias, such as > 1V, can yield sufficiently low contact resistance when using a high-. back gate oxide.

A novel technique, called Fermi-Dirac (FD)-function method, is proposed for extracting channel mobility (mu(CH)) and parasitic resistance (R-p) of 2-D material (2DM) MOSFETs. The functional form of this method is formalized using three (two) parameters for describing the gate bias-dependent mu(CH)(R-p) of a back gate (BG) and top gate (TG) 2-D MOSFET. The method is successfully demonstrated by uniquely extracting these parameters from an antimony (Sb) contacted MoS(2 )BG-MOSFET experimental data. Also demonstrated our FD-function method on palladium (Pd) contacted WSe2 top-gated BG-MOSFET experiments. The extraction accuracy is tested against experiment calibrated TCAD simulations with widely different mu(CH) and R-p. These tests show mu(CH) andR(p) extraction errors within $\pm$ 10% and +/- 8%, respectively. Thus, the proposed FD-function method is highly accurate enables fast extraction and can be easily incorporated in the routine industrial wafer acceptance testing (WAT).

We present a modelling framework that enables efficient exploration of the electrical performance of devices based on 2D material vertical heterojunctions. Electronic structure data from density functional theory (DFT) simulations is used to extract parameters for k.p Hamiltonians. Material models are then employed in device simulations based on non-equilibrium Green's functions (NEGF) for a quantum-mechanical description of charge transport. Electron-phonon scattering is included in order to account for dissipative phenomena as well as phonon-assisted interlayer charge transport. We demonstrate our methodology with an application to a Dirac-source field-effect transistor (DS-FET) design based on a monolayer molybdenum disulfide channel (ML-MoS2) with a graphene contact.

2D transition metal dichalcogenides (TMDs) show promise for transistor scaling, but their on-scale performance had not been proven yet. This work demonstrates contact length (Lc) scaling while holding a low contact resistance (R C ) down to 11 nm. Channel length $(\mathrm{L}_{\text{CH}})$ scaling shows I ON can increase down to at least 12 nm with low Rc. The very scaled $(\mathrm{L}_{\text{CH }}=19$ nm and $\mathrm{L}_{\mathrm{C}}=12$ nm) Mos2 transistor with Sb-based metal contact has current density of ~1130 μA/μm at $\mathrm{V}_{\text{DS}}$ = 1 V, and a low $\mathrm{R}_{C}$ of ~ 190 Ω.μm. These scaled transistors, processed within a back-end-of-line (BEOL) thermal budget, do not exhibit subthreshold swing (S.S.) degradation or observable drain-induced barrier lowering (DIBL) down to $\mathrm{L}_{\text{CH}}=12\text{nm}$ .

A comprehensive quantitative root cause study of defect evolution leading to memory window closure from a charge balance and charge trapping perspective throughout all phases of a Si channel Hf0.5Zr0.5O2 (HZO) ferroelectric field-effect-transistor (FEFET) is reported. Starting with the first write pulse, an excessive SiO2 interlayer field is revealed that triggers the creation of defect levels Dit in excess of 1015 cm−2 eV−1 at the HZO–SiO2 interface screening ferroelectric (FE) polarization while enabling FE switching. Under subsequent early bipolar fatigue cycling (up to 104 cycles), defect creation commences at the SiO2–Si interface due to the high injected hole fluence (0.39 C/m2) during each stress pulse causing negative bias instability (NBI), which shifts the threshold voltage of the erase state VT,ERS by −0.3 V with accrual of permanently captured charge Nit of up to +5 × 10−3 C/m2 (3 × 1012 cm−2). Subsequently, Nit NBI generation at the SiO2–Si interface accelerates reaching levels of +7 × 10−2 C/m2, locking both FEFET program and erase drain current vs gate–source-voltage (ID–VGS) characteristics in the FEFET on-state inducing memory window closure at 105 cycles while FE switching (switched polarization Psw = 0.34 C/m2) remains essentially intact. These findings guide the down-selection toward suitable semiconductor/FE systems for charge balanced, reliable, and high endurance FEFETs.

In this theoretical study, we compare electrostatically doped metal-transition metal dichalcogenide (TMD) edge-contacts versus substitutionally doped edge-contacts in terms of their contact resistance. Our approach involves the utilization of electrostatic doping achieved by applying back-gate bias to the metal-TMD edge contacts, where carrier injection is primarily governed by the Schottky barrier at the interface. To analyze these contacts, we employ the Wentzel-Kramers-Brillouin (WKB) approximation to calculate the transmission coefficient and use density functional theory (DFT)-derived band structures. We numerically solve the Poisson equation to capture the electrostatic potential. We also account for the impact of the image force using Green's function for the Poisson equation with boundary conditions appropriate to our specific geometry. Our findings reveal that electrostatically doped TMD edge contacts exhibit higher contact resistance compared to impurity-doped edge contacts at equivalent carrier concentrations. At the same time, we find that, among the electrostatically doped edge contacts, a low-κ back-gate oxide in conjunction with low-κ top oxide is preferable in terms of improvement in contact resistance. For instance, in a metal-TMD edge contact scenario involving a monolayer MoS2 as the channel, SiO2 as the infinitely thick top oxide, and a SiO2 back-gate oxide with an equivalent oxide thickness (EOT) of 1nm, we demonstrate that it is possible to achieve an impressively low contact resistance of 50Ωµm when the back-gate bias exceeds or equals 2 V. Published by the American Physical Society 2024

We calculate the contact resistance for an edge- and top-contacted 2D semiconductor. The contact region consists of a metal contacting a monolayer of MoS 2 which is otherwise surrounded by SiO 2 . We use the quantum transmitting boundary method to compute the contact resistance as a function of the 2D semiconductor doping concentration. An effective mass Hamiltonian is used to describe the properties of the various materials. The electrostatic potentials are obtained by solving the Poisson equation numerically. We incorporate the effects of the image-force barrier lowering on the Schottky barrier and examine the impact on the contact resistance. At low doping concentrations, the contact resistance of the top contact is lower compared to edge contact, while at high doping concentrations, the edge contact exhibits lower resistance.

High-performance and scaled transistors on carbon nanotube (CNT) channel are enabled by the quality of device component modules. This paper advances each module by single-CNT control experiments reporting: (1) remarkable n-type contact resistance of 5.1 k$\Omega$/CNT(20.4$\Omega-\mu$m for 250 CNT/$\mu$m) at 20 nm contact length, (2) tunable N-and Pdoping of CNT with dielectric doping, (3) improvement in top-gate dielectric interface to CNT by channel cleaning, (4) demonstration of channel comprised of dense CNT array with reduced bundle density, and (5) analysis of CNT bandgap tradeoffs with variability control strategy. The first component-complete pMOS FET is demonstrated on high-density CNTs with up to 680 $\mu$A/$\mu$m at -0.7V VDS.

We present dielectric barrier booster for remote extension doping in low-dimensional materials (LDMs), e.g., ID Carbon Nanotubes (CNTs) and 2D MoS 2 . In contrast to prior work, the key idea is to "engineer" the thickness of a barrier layer (t BAR ) between LDM and dopant layer, in conjunction with the dopant layer itself, to optimize various remote extension doping trade-offs (e.g., transport, leakage, doping strength, parasitic load). Understanding such trade-offs requires extensive Design-Technology Co-Optimization (DTCO), not explored in prior literature. We explore a large space of ~50,000 design points through DTCO and derive various insights, including: (a) Barrier booster is key to enabling up to 1.5× energy-delay product (EDP) benefits for CNT FET ring oscillators vs. no-barrier case, (b) Barrier booster optimization depends on the target objective function: EDP optimization favors small t BAR (to increase extension charge density) while delay optimization favors large t BAR (to improve transport properties), (c) Doping guidelines derived from DTCO are LDM-specific: for example, we project 1.9× and 4.6× EDP benefits for extension-doped (with barrier booster) CNTs and MoS 2 , respectively, vs. undoped FETs. However, if EDP-optimal parameters for MoS 2 are used for CNTs (or vice-versa), the resulting EDP benefits are <1%.

We examine the dependence of source-to-drain tunneling (SDT) leakage on the effective channel length (L eff ) for Si and Ge pMOS with L eff ranging from 5 nm to 20 nm. The subband Boltzmann transport equation is solved including the SDT process, which is evaluated from the WKB approximation. Device architectures including nanosheet transistors (NSTs) and nanowire transistors (NWTs) with the proper specification are analyzed. The results show that SDT becomes a serious concern for Ge pNSTs with L eff lower than 17 nm. However, such leakage degradation from SDT, can be further mitigated by optimizing the cross-sectional configuration.