For the time being, ΔΣ ADCs used in the space environment mainly target applications in the LF band. This paper presents a research project that explores a ΔΣ ADC architecture for operation in the MF/HF bands. The SG13RH technology, that offers characterization data under radiation and hardened devices, was selected to implement the test vehicles of this research. Additionally, the suitability of the proposed architecture for a future migration to ultra-deep submicron CMOS nodes is also considered.

This work presents the status of the TM/TC MS-ASIC development (telemetry and telecommand mixed-signal application specific integrated circuit) and describes its final implemented features and target applications. Its usage in RIU/RTU and ICU satellite subsystems will entail weight, volume, and price reduction, in line with the market trend of reduced-size satellite fleets.

Infrared imaging technology, used both to study deep-space bodies' radiation and environmental changes on Earth, experienced constant improvements in the last few years, pushing data converter designers to face new challenges in terms of speed, power consumption and robustness against extremely harsh operating conditions. This paper presents a 96.6-dB-SNDR (Signal-to-Noise-plus-Distortion Ratio) 50-kHz-bandwidth fourth-order single-bit switched-capacitor delta-sigma modulator for ADC operating at 1.8 V and consuming 7.9 mW fit for space instrumentation. The circuit features novel Class-AB single-stage switched variable-mirror amplifiers (SVMAs) enabling low-power operation, as well as low sensitivity to both process and temperature deviations for the whole modulator. The physical implementation resulted in a 1.8-mm2 chip integrated in a standard 0.18-µm 1-poly-6-metal (1P6M) CMOS technology, and it reaches a 164.6-dB Schreier figure of merit from experimental SNDR measurements without making use of any clock bootstrapping,analogcalibration,nordigitalcompensationtechnique. Whencoupledtoa2048×2048 IR imager, the current design allows more than 50 frames per minute with a resolution of 16 effective number of bits (ENOB) while consuming less than 300 mW.

In the radiation environment envisaged for the interplanetary mission to Jupiter named Juice, the electronic equipment will require to withstand up to 300krad of Total Ionization Dose. The availability of high performance components that can cope with that requirement is low or non-existent and for that reason ESA funded an activity to create radiation tolerant high-performance mixed-signal IPs. In the frame of the project two different ASICs where implemented: A rad-hard programmable ∑∆ modulator (CVB-001) which contains four separate ∑∆ modulator and a Rad-hard analogue front-end chip (CVC-001) which contains a Bessel Filter, a Digital to Analogue Converter, a Low Noise Amplifier and a Power amplifier. Simulation and validation results of those chips and in particular the detailed behaviour of each of the IPs will be presented.

High-resolution Sigma-Delta (ΣΔ) ADCs are increasingly used in portable medical applications for the measurement of biopotential signals. This paper presents the implementation and measurements of a novel ultra-low power low voltage multi-bit continuous-time sigma-delta (CT-ΣΔ) modulator, whose quantizer and feedback DACs operate in the time domain. Instead of the conventional flash quantizer and mismatch corrected multi-bit feedback DACs, a Dual-Slope (DS) quantizer and a Pulse-Width Modulated (PWM) DACs have been adopted in this design. The modulator has been implemented in a standard 0.18μm CMOS technology and features 83dB dynamic-range (DR) for a signal bandwidth of 256Hz. When clocked at 917kHz it consumes 13.3μW from a 1.4V supply.

This paper presents the system level design of a novel multi-bit Sigma-Delta (ΣΔ) ADC architecture that replaces the flash quantizer and mismatch corrected multi-bit DAC of a ΣΔ modulator by an integrating quantizer and a Pulse-Width Modulated DAC. This converter achieves the resolution of a multi-bit design using single-bit circuitry. The quantizer of this modulator is similar to a classical Dual-Slope integrating converter, but the charge residue in the integrator at the end of each conversion cycle is stored for the next conversion, providing first order noise shaping. As an example, the system level performance of a second-order multi-bit ¿¿ ADC using this new architecture has been evaluated. Also, circuit level specifications have been established, considering the most critical circuit non-idealities. The behavioral simulation results show that the ADC could achieve an ENOB = 13 bits in a signal bandwidth of 2 MHz using conventional CMOS technology, which could be suitable for wireless communication standards.

The ADC shown in this paper uses an innovative Sigma-Delta (Sigma Delta) architecture that replaces the flash quantizer and mismatch corrected DAC of a multibit continuous time (CT) modulator by a time domain encoder similar to a PWM modulator to reduce the effective ADC area. The modulator achieves the resolution of a multibit design using single bit circuitry by concentrating most of the quantization error energy around a single frequency, which is afterwards removed, seizing the zeros of a sinc decimation filter. The non flat error spectrum is accomplished by use of two filter loops, one of which is made to operate in a self-oscillating mode. An experimental CT-Sigma Delta ADC prototype has been fabricated in 0.13 mu m CMOS which implements a third order modulator with two operating modes. Measurements show an effective number of bits (ENOB) of 10 bits and 12 bits in a signal bandwidth of 17 MHz and 6.4 MHz, respectively, and a power-efficient figure of merit (FoM = P wr/2 . BW . 2(ENOB)) of 0.48 pJ/conversion at 1.5 V supply. The active area of the ADC is 0.105 mm(2).

This paper shows the operating principle and experimental results of a new continuous-time sigma-delta modulator architecture. The proposed modulator does not require a multibit quantizer nor a mismatch-shaping digital-to-analog converter to produce a multibit noise-shaped output. Instead, its quantizer encodes the loop filter output in a binary signal using a time encoding technique similar to pulsewidth modulation. This binary signal is used to generate both the analog feedback loop signal and the digital output. A proof-of-concept chip in 0.35-mum CMOS achieves 10 bits of resolution within a signal bandwidth of 1.2 MHz using a first-order modulator.