We systematically investigate the interplay between materials engineering, quantum transport, and low-frequency charge noise in silicon metal–oxide–semiconductor (SiMOS) quantum devices. By combining Hall-bar transport measurements with charge-noise spectroscopy of gate-defined quantum dots, we identify correlations between gate-stack design, carrier mobility, and electrostatic noise, providing an experimental case study of material and process dependencies relevant to low-noise, high-mobility operation. Hall-bar studies reveal that increasing the atomic-layer-deposition temperature of Al_2O_3 markedly enhances mobility, whereas the choice of oxidant has little impact. Devices incorporating HfO_2 exhibit improved carrier mobility, an interesting observation that can plausibly be attributed to defect passivation associated with aluminum diffusion from the gate metal into the HfO_2 layer. Charge-noise measurements show a strong correlation between higher mobility and reduced noise, with TiPd-gated devices displaying both degraded transport and elevated charge noise. In contrast, the poly-Si-gated CMOS-foundry device achieves the lowest noise levels. Finally, dual-feedback dot–sensor stability mapping demonstrates enhanced charge stability in devices with the gate stacks studied here, underscoring their promise for scalable, high-fidelity silicon spin-qubit platforms.

Single nuclear spins in silicon are a promising resource for quantum technologies due to their long coherence times and excellent control fidelities. Qubits and qudits have been encoded on donor nuclei, with successful demonstrations of Bell states and quantum memories on the spin- / 2 1 P 31 and cat-qubits on the spin- / 2 7 Sb 123 nuclei. Isoelectronic nuclear spins coupled to gate-defined quantum dots, such as the naturally occurring Si 29 isotope, possess no additional charge and allow for the coupled electron to be shuttled without destroying the nuclear spin coherence. Here, we demonstrate the coupling of a spin- / 2 9 Ge 73 nuclear spin to a gate-defined quantum dot in SiMOS via Pauli spin blockade readout using rf reflectometry. We observe the hyperfine interaction (HFI) to the coupled quantum dot electron and are able to tune it from 180 to 350 kHz, through the voltages applied to the lateral gate electrodes. This smaller HFI combined with the faster readout enable easier quantum nondemolition readout of the nuclear spin state. Thus, this work lays the foundation for future spin control experiments on the spin- / 2 9 qudit as well as more advanced experiments such as entanglement distribution between distant nuclear spins or repeated weak measurements.

Several domains of society will be disrupted once millions of high-quality qubits can be brought together to perform fault-tolerant quantum computing (FTQC). All quantum computing hardware available today is many orders of magnitude removed from the requirements for FTQC. The intimidating challenges associated with integrating such complex systems have already been addressed by the semiconductor industry -hence many qubit makers have retrofitted their technology to be CMOS-compatible. This compatibility, however, can have varying degrees ranging from the mere ability to fabricate qubits using a silicon wafer as a substrate, all the way to the co-integration of qubits with high-yield, low-power advanced electronics to control these qubits. Extrapolating the evolution of quantum processors to future systems, semiconductor spin qubits have unique advantages in this respect, making them one of the most serious contenders for large-scale FTQC. In this review, we focus on the overlap between state-of-the-art semiconductor spin qubit systems and CMOS industry Very Large-Scale Integration (VLSI) principles. We identify the main differences in spin qubit operation, material, and system requirements compared to well-established CMOS industry practices. As key players in the field are looking to collaborate with CMOS industry partners, this review serves to accelerate R D towards the industrial scale production of FTQC processors.

Silicon spin qubits are a promising platform for quantum computing due to their high coherence, controllability, and CMOS manufacturability, yet scalable implementations have so far been limited to a few qubits. Here, to take a step towards larger qubit systems, we tune and coherently control an eight-dot linear array of silicon spin qubits fabricated in a 300 mm CMOS-compatible foundry process, establishing operational scalability beyond the two-qubit regime. All eight qubits are successfully tuned and characterized as four double-dot pairs, exhibiting Ramsey dephasing times T 2 * up to 41(2) μs and Hahn-echo coherence times T 2 Hahn up to 1.31(4) ms. Readout of the central four qubits is achieved via a cascaded charge-sensing protocol, enabling high-fidelity measurements of the entire multi-qubit array in a two step process. Additionally, we demonstrate a two-qubit gate operation between adjacent qubits with low phase noise. We show that silicon spin qubit arrays can be scaled to medium-sized arrays of 8 qubits while maintaining system coherence.

Silicon spin qubits are a leading candidate for large-scale quantum computing owing to their compatibility with semiconductor manufacturing. However, scaling to useful fault-tolerant processors will likely generate thermal loads that exceed the cooling power available at millikelvin temperatures. Raising the operating temperature eases cooling requirements but reduces gate fidelity, increasing the overhead of quantum error correction. Identifying the operating temperature that minimizes total power consumption is therefore a key challenge for commercially viable quantum computers. Here, we use gate set tomography to benchmark two-qubit silicon chips fabricated in both industrial and academic environments over a range of temperatures. Elevated temperatures substantially shorten coherence times and increase gate and state-preparation-and-measurement infidelities. Based on these measurements, we develop a general power model for silicon quantum computers that combines cryogenic cooling requirements with error-correction overheads. We show that a finite optimal operating temperature exists and is strongly influenced by a crossover temperature near 1 K in current devices, above which gate fidelity degrades rapidly. These results connect device-level fidelity limitations to system-level power requirements, providing design guidelines for large-scale silicon quantum computers.

Many technologies require a precise electrical current standard that at present is achieved indirectly through voltage and resistance standards. Silicon-based charge pumps could provide a direct electrical standard that scales inherently through their compatibility with complementary metal oxide semiconductor (CMOS) fabrication methods. However, coherent quantized charge transfer has so far been demonstrated only in nanoscale devices that are custom-fabricated in academic cleanrooms or research technology foundries. Here, we show that a CMOS device manufactured with a commercial 22 nm process node can be used to realize a quantum current standard in the International System of Units (SI). We measure the accuracy of two parallel-connected charge pumps with reference to SI-traceable voltage and resistance standards in a pumped helium system. This translation of low-temperature quantum effect device concepts from scientific research into an industrial fabrication context opens a path toward advancing quantum electrical metrology and quantum hardware engineering.

Quantum computation with electron spin qubits requires coherent and efficient manipulation of these spins, typically accomplished through the application of alternating magnetic or electric fields for electron spin resonance. In particular, electrical driving allows us to apply localized fields on the electrons, which benefits scale-up architectures. However, we have found that Electric Dipole Spin Resonance is insufficient for modeling the Rabi behavior in recent experimental studies. Therefore, we propose that the electron spin is being driven by a method of electric spin qubit control that generalizes the spin dynamics by taking into account a quadrupolar contribution of the quantum dot: electric quadrupole spin resonance. In this work, we explore the electric quadrupole driving of a quantum dot in silicon, specifically examining the cases of 5 and 13 electron occupancies.

Among the many types of qubit presently being investigated for a future quantum computer, silicon spin qubits with millions of qubits on a single chip are uniquely positioned to enable quantum computing. However, it has not been clear whether the outstanding high-fidelity operations and long coherence times shown by silicon spin qubits fabricated in academic settings1-8 can be reliably reproduced when the qubits are manufactured in a semiconductor foundry9-11. Here we show precise qubit operation of silicon two-qubit devices made with standard semiconductor tooling in a 300-mm foundry environment. Of the key metrics, single- and two-qubit control fidelities exceed 99% for all four devices, and the state preparation and measurement fidelities reach up to 99.9%, as evidenced by gate set tomography. We report spin lifetime and coherence up to T1 = 9.5 s, T 2 * = 40.6 μ s and T 2 Hahn = 1.9 ms . We determine that residual nuclear spin-carrying isotopes contribute substantially to operational errors, identifying further isotopic purification as a clear pathway to even higher performance.

Recent advances in semiconductor spin qubits have enabled linear arrays with more than 10 qubits. Scaling to two-dimensional (2D) arrays is essential for fault-tolerant implementations but introduces significant fabrication challenges due to the increased density of the gate electrodes. Moreover, implementing two-qubit entanglement control requires the addition of interstitial exchange gates between quantum dots in this dense gate structure. In this work, we present a 2D array of silicon metal-oxide-semiconductor (MOS) quantum dots with tunable interdot coupling between all neighboring dots. Characterized at 4.2 K, the device exhibits exceptional tunability, supports the formation and isolation of both double- and triple-dot configurations, and achieves tunnel coupling control spanning up to 30 decades per volt. These results provide critical technical feedback and a foundational benchmark for advancing MOS spin qubit technology into the 2D regime.

Recent advances in semiconductor spin qubits have achieved linear arrays exceeding ten qubits. Moving to two-dimensional (2D) qubit arrays is a critical next step to advance towards fault-tolerant implementations, but it poses substantial fabrication challenges, particularly because enabling control of nearest-neighbor entanglement requires the incorporation of interstitial exchange gates between quantum dots in the qubit architecture. In this work, we present a 2D array of silicon metal-oxide-semiconductor (MOS) quantum dots with tunable interdot coupling between all adjacent dots. The device is characterized at 4.2 K, where we demonstrate the formation and isolation of double-dot and triple-dot configurations. We show control of all nearest-neighbor tunnel couplings spanning up to 30 decades per volt through the interstitial exchange gates and use advanced modeling tools to estimate the exchange interactions that could be realized among qubits in this architecture. These results represent a significant step towards the development of 2D MOS quantum processors compatible with foundry manufacturing techniques.

Quantum computers leverage entanglement to achieve superior computational power. However, verifying that the entangled state does not follow the principle of local causality has proven difficult for spin qubits in gate-defined quantum dots, as it requires simultaneously high concurrence values and readout fidelities to break the classical bound imposed by Bell's inequality. While low error rates for state preparation, control, and measurement have been independently demonstrated, a simultaneous demonstration remained challenging. We employ advanced protocols like heralded initialization and calibration via gate set tomography (GST), to push fidelities of the full 2-qubit gate set above 99%, including state preparation and measurement (SPAM). We demonstrate a 97.17% Bell state fidelity without correcting for readout errors and violate Bell's inequality using direct parity readout with a Bell signal of S = 2.731. Our measurements exceed the classical limit even at 1.1 K or entanglement lifetimes of 100 μs. Violating Bell's inequality in a silicon quantum dot qubit system is a key milestone, as it proves quantum entanglement, fundamental to achieving quantum advantage.

A key virtue of spin qubits is their sub-micron footprint, enabling a single silicon chip to host the millions of qubits required to execute useful quantum algorithms with error correction1-3. However, with each physical qubit needing multiple control lines, a fundamental barrier to scale is the extreme density of connections that bridge quantum devices to their external control and readout hardware4-6. A promising solution is to co-locate the control system proximal to the qubit platform at milli-kelvin temperatures, wired up by miniaturized interconnects7-10. Even so, heat and crosstalk from closely integrated control have the potential to degrade qubit performance, particularly for two-qubit entangling gates based on exchange coupling that are sensitive to electrical noise11,12. Here we benchmark silicon metal-oxide-semiconductor (MOS)-style electron spin qubits controlled by heterogeneously integrated cryo-complementary metal-oxide-semiconductor (cryo-CMOS) circuits with a power density sufficiently low to enable scale-up. Demonstrating that cryo-CMOS can efficiently perform universal logic operations for spin qubits, we go on to show that milli-kelvin control has little impact on the performance of single- and two-qubit gates. Given the complexity of our sub-kelvin CMOS platform, with about 100,000 transistors, these results open the prospect of scalable control based on the tight packaging of spin qubits with a 'chiplet-style' control architecture.

Commercially viable quantum computing will require large numbers of high-quality qubits. Therefore, leveraging the extensive capabilities of conventional CMOS technology is expected to accelerate the development of a fault-tolerant quantum computer. Here we report on the highest single-qubit control fidelity of 99.9% for any Si/SiO2 spin qubit fabricated in a 300 mm wafer process. This result represents an important milestone towards a large-scale silicon quantum processor on a single chip.

Superior computational power promised by quantum computers utilises the fundamental quantum mechanical principle of entanglement. However, achieving entanglement and verifying that the generated state does not follow the principle of local causality has proven difficult for spin qubits in gate-defined quantum dots, as it requires simultaneously high concurrence values and readout fidelities to break the classical bound imposed by Bell's inequality. Here we employ heralded initialization and calibration via gate set tomography (GST), to reduce all relevant errors and push the fidelities of the full 2-qubit gate set above 99

Spins of electrons in CMOS quantum dots combine exquisite quantum properties and scalable fabrication. In the age of quantum technology, however, the metrics that crowned Si/SiO2 as the microelectronics standard need to be reassessed with respect to their impact upon qubit performance. We chart the spin qubit variability due to the unavoidable atomic-scale roughness of the Si/SiO$_2$ interface, compiling experiments in 12 devices, and developing theoretical tools to analyse these results. Atomistic tight binding and path integral Monte Carlo methods are adapted for describing fluctuations in devices with millions of atoms by directly analysing their wavefunctions and electron paths instead of their energy spectra. We correlate the effect of roughness with the variability in qubit position, deformation, valley splitting, valley phase, spin-orbit coupling and exchange coupling. These variabilities are found to be bounded and lie within the tolerances for scalable architectures for quantum computing as long as robust control methods are incorporated.

Achieving high-fidelity entangling operations between qubits consistently is essential for the performance of multi-qubit systems. Solid-state platforms are particularly exposed to errors arising from materials-induced variability between qubits, which leads to performance inconsistencies. Here we study the errors in a spin qubit processor, tying them to their physical origins. We use this knowledge to demonstrate consistent and repeatable operation with above 99% fidelity of two-qubit gates in the technologically important silicon metal-oxide-semiconductor quantum dot platform. Analysis of the physical errors and fidelities in multiple devices over extended periods allows us to ensure that we capture the variation and the most common error types. Physical error sources include the slow nuclear and electrical noise on single qubits and contextual noise that depends on the applied control sequence. Furthermore, we investigate the impact of qubit design, feedback systems and robust gate design to inform the design of future scalable, high-fidelity control strategies. Our results highlight both the capabilities and challenges for the scaling-up of silicon spin-based qubits into full-scale quantum processors. For solid-state qubits, the material environment hosts sources of errors that vary in time and space. This systematic analysis of errors affecting high-fidelity two-qubit gates in silicon can inform the design of large-scale quantum computers.

A key virtue of spin qubits is their sub-micron footprint, enabling a single silicon chip to host the millions of qubits required to execute useful quantum algorithms with error correction. With each physical qubit needing multiple control lines however, a fundamental barrier to scale is the extreme density of connections that bridge quantum devices to their external control and readout hardware. A promising solution is to co-locate the control system proximal to the qubit platform at milli-kelvin temperatures, wired-up via miniaturized interconnects. Even so, heat and crosstalk from closely integrated control have potential to degrade qubit performance, particularly for two-qubit entangling gates based on exchange coupling that are sensitive to electrical noise. Here, we benchmark silicon MOS-style electron spin qubits controlled via heterogeneously-integrated cryo-CMOS circuits with a low enough power density to enable scale-up. Demonstrating that cryo-CMOS can efficiently enable universal logic operations for spin qubits, we go on to show that mill-kelvin control has little impact on the performance of single- and two-qubit gates. Given the complexity of our milli-kelvin CMOS platform, with some 100-thousand transistors, these results open the prospect of scalable control based on the tight packaging of spin qubits with a chiplet style control architecture.

High fidelity qubit readout is critical in order to obtain the thresholds needed to implement quantum error correction protocols and achieve fault-tolerant quantum computing. Large-scale silicon qubit devices will have densely-packed arrays of quantum dots with multiple charge sensors that are, on average, farther away from the quantum dots, entailing a reduction in readout fidelities. Here, we present a readout technique that enhances the readout fidelity in a linear SiMOS 4-dot array by amplifying correlations between a pair of single-electron transistors, known as a twin SET. By recording and subsequently correlating the twin SET traces as we modulate the dot detuning across a charge transition, we demonstrate a reduction in the charge readout infidelity by over one order of magnitude compared to traditional readout methods. We also study the spin-to-charge conversion errors introduced by the modulation technique, and conclude that faster modulation frequencies avoid relaxation-induced errors without introducing significant spin flip errors, favouring the use of the technique at short integration times. This method not only allows for faster and higher fidelity qubit measurements, but it also enhances the signal corresponding to charge transitions that take place farther away from the sensors, enabling a way to circumvent the reduction in readout fidelities in large arrays of qubits.

Fabrication of quantum processors in advanced 300 mm wafer-scale complementary metal-oxide-semiconductor (CMOS) foundries provides a unique scaling pathway towards commercially viable quantum computing with potentially millions of qubits on a single chip. Here, we show precise qubit operation of a silicon two-qubit device made in a 300 mm semiconductor processing line. The key metrics including single- and two-qubit control fidelities exceed 99

The encoding of qubits in semiconductor spin carriers has been recognized as a promising approach to a commercial quantum computer that can be lithographically produced and integrated at scale 1 – 10 . However, the operation of the large number of qubits required for advantageous quantum applications 11 – 13 will produce a thermal load exceeding the available cooling power of cryostats at millikelvin temperatures. As the scale-up accelerates, it becomes imperative to establish fault-tolerant operation above 1 K, at which the cooling power is orders of magnitude higher 14 – 18 . Here we tune up and operate spin qubits in silicon above 1 K, with fidelities in the range required for fault-tolerant operations at these temperatures 19 – 21 . We design an algorithmic initialization protocol to prepare a pure two-qubit state even when the thermal energy is substantially above the qubit energies and incorporate radiofrequency readout to achieve fidelities up to 99.34% for both readout and initialization. We also demonstrate single-qubit Clifford gate fidelities up to 99.85% and a two-qubit gate fidelity of 98.92%. These advances overcome the fundamental limitation that the thermal energy must be well below the qubit energies for the high-fidelity operation to be possible, surmounting a main obstacle in the pathway to scalable and fault-tolerant quantum computation.