Electron spin resonance spectroscopy (ESR) of a single electron in planar Si-MOS quantum dot is reported in the vicinity of a valley level anti-crossing. A number of one and two-photon resonances are observed due to mixing of magnetic spin-flip and electric valley-flip transitions. This allows the reconstruction of the energy-level diagram of a four state system with two valley and two spin states. Near the anti-crossing, an enhancement of the Rabi frequency is observed. This is attributed to an electric-dipole transition activated by admixing of the upper energy level due to inter-valley spin coupling. The electric-dipole transition may be driven via capacitive coupling between the ESR antenna, and the confinement gate. To characterize spin-valley coupling responsible for the enhancement, we measure the anisotropy of the g-factor difference between the two valley states, the mean g-factor and the inter-valley spin coupling for both in and out-of-plane magnetic fields. The inter-valley spin coupling is strongly modulated by the direction of the B-field, and is strongest for out-of-plane B-field, consistent with an in-plane spin-valley field. In principle, this strong Electric dipole spin resonance (EDSR) effect could be utilized for fast all-electrical spin control in small-scale devices.

Achieving uniform and scalable control of semiconductor spin qubits remains a key challenge for large scale quantum computing. In this work, we investigate how gate oxide thickness influences uniformity in dense two dimensional silicon quantum dot arrays. Using a 7 x 7 array fabricated in a 300 mm CMOS-process patterned by EUV lithography, we statistically characterize 392 quantum dots across four different oxide thicknesses. The threshold voltages, capacitances, lever arms, and charging energies are extracted using parallel row based measurements and we identify an optimal SiO2 thickness of 17 nm that minimizes threshold voltage variability below 63 mV standard deviation. Our observations illustrate how multiple sources of disorder can introduce competing oxide-thickness dependencies, resulting in non-monotonic trends. These results provide key design guidelines for dense, scalable silicon spin qubit architectures.

Silicon spin qubits are a promising platform for quantum computing due to their high coherence, controllability, and CMOS manufacturability, yet scalable implementations have so far been limited to a few qubits. Here, to take a step towards larger qubit systems, we tune and coherently control an eight-dot linear array of silicon spin qubits fabricated in a 300 mm CMOS-compatible foundry process, establishing operational scalability beyond the two-qubit regime. All eight qubits are successfully tuned and characterized as four double-dot pairs, exhibiting Ramsey dephasing times T 2 * up to 41(2) μs and Hahn-echo coherence times T 2 Hahn up to 1.31(4) ms. Readout of the central four qubits is achieved via a cascaded charge-sensing protocol, enabling high-fidelity measurements of the entire multi-qubit array in a two step process. Additionally, we demonstrate a two-qubit gate operation between adjacent qubits with low phase noise. We show that silicon spin qubit arrays can be scaled to medium-sized arrays of 8 qubits while maintaining system coherence.

The rate of coherence loss is lower for a qubit under the Rabi drive than a freely evolving qubit T-2(Rabi )> T-2(& lowast;) . Building on this principle, concatenated continuous driving (CCD) keeps the qubit under continuous drive to suppress noise and manipulate dressed states by either phase or amplitude modulation. In this work, we propose a variant of CCD which simultaneously modulates both the amplitude and phase of the driving field to generate a circularly polarized field in the rotating frame of the carrier frequency. This circular-modulated CCD (CMCCD) cancels the counterrotating term in the second rotating frame, eliminating a systematic pulse-area error that arises from an imperfect rotating wave approximation for fast gates. Numerical simulations demonstrate that the proposed CMCCD achieves higher gate fidelity than conventional CCD schemes. We further implement and compare different CCD protocols using an electron spin-qubit in an isotopically purified Si-28-MOS quantum dot and evaluate its robustness by applying static detuning and Rabi frequency errors. The robustness is significantly improved compared with the standard Rabi drive, showing the effectiveness of this scheme for qubit arrays with variation in qubit frequency, coupling to the Rabi drive, and low-frequency noise. The proposed scheme can be applied to various physical systems, including trapped atoms, cold atoms, superconducting qubits, and NV centers.

Among the many types of qubit presently being investigated for a future quantum computer, silicon spin qubits with millions of qubits on a single chip are uniquely positioned to enable quantum computing. However, it has not been clear whether the outstanding high-fidelity operations and long coherence times shown by silicon spin qubits fabricated in academic settings1-8 can be reliably reproduced when the qubits are manufactured in a semiconductor foundry9-11. Here we show precise qubit operation of silicon two-qubit devices made with standard semiconductor tooling in a 300-mm foundry environment. Of the key metrics, single- and two-qubit control fidelities exceed 99% for all four devices, and the state preparation and measurement fidelities reach up to 99.9%, as evidenced by gate set tomography. We report spin lifetime and coherence up to T1 = 9.5 s, T 2 * = 40.6 μ s and T 2 Hahn = 1.9 ms . We determine that residual nuclear spin-carrying isotopes contribute substantially to operational errors, identifying further isotopic purification as a clear pathway to even higher performance.

We demonstrate high-fidelity single qubit control in a natural Si-MOS quantum dot fabricated in an industrial 300 mm wafer process on a silicon on insulator (SOI) wafer using electron spin resonance. A relatively high optimal Rabi frequency of 5 MHz is achieved, dynamically decoupling the electron spin from its 29-Si environment. Tracking the qubit frequency reduces the impact of low frequency noise in the qubit frequency and improves the T^Rabi from 7 to 11 μs at a Rabi frequency of 5 MHz, resulting in Q-factors exceeding 50. Randomized benchmarking returns an average single gate control fidelity of 99.5 ± 0.3

Fabrication of quantum processors in advanced 300 mm wafer-scale complementary metal-oxide-semiconductor (CMOS) foundries provides a unique scaling pathway towards commercially viable quantum computing with potentially millions of qubits on a single chip. Here, we show precise qubit operation of a silicon two-qubit device made in a 300 mm semiconductor processing line. The key metrics including single- and two-qubit control fidelities exceed 99

In line Electrical measurement (E-Test) are the most effective predictors for EOL yield control. As technology progress with scaling, the number. of process layers increases, allowing in-line electrical measurements only after several months since lot started process in-line. As a result, each E-Test monitor controls longer and more challenging process loop. Most of the in-line pattern control that impact electrical performance measured separately for each pattern polygon and material properties. In addition, Edge Placement Error (EPE) methodology, allows combination of multiple dimensions like CD, Overlay and LER measurements to better predict yield impact. Technology shrinkage, resulting that transistor electrical performance, defined by more geomaterial parameters as well as material compositions and defectivity. In this paper we demonstrate a direct prediction from high resolution Scanning Electron Microscope (SEM) images to the first inline electrical measurement (M1) using Deep Learning (DL) techniques. The DL model provide early prediction of electrical performance, describing accurately Within Wafer (WIW) variation weeks earlier than the actual electrical measurements. Multiple layers prediction may indicate suspected process loop that modulate majority of variation and save time to solution. It can be achieved since the DL model utilizes complementary information exist on the full e-Beam image like materials and defectivity. The following results will indicate that accumulating information collected from several layers will improve prediction sensitivity and lead to even more accurate prediction capabilities. We assume that the effectiveness of the proposed prediction method will increase with process complexity, since the modulation of the existing yield predictors is losing sensitivity as design rule shrinks. In addition, since fabrication phase gets longer, the time to actual electrical measurements increase, making an early, nondestructive, and accurate prediction for electrical performance more and more valuable.

Self-Aligned Quadruple Patterning (SAQP) is used in advanced CMOS-FET technologies to enable the formation of arrays of fins at sub-40 nm pitches. As these technology nodes keep scaling down and the fins get taller for performance improvement, the patterns become denser and present very high aspect ratio (HAR). The scaling trends make the fin pattern more subject to mechanical instabilities during the processing steps. We describe in this paper a specific mechanical fin bending mode linked to the SAQP scheme targeting 24 nm pitch, the HAR and the formation and recess steps of the isolating oxide. We investigated the evolution of fin bending throughout the fin and isolation formation. We observed fins start bending at the FCVD deposition step exhibiting rotation angles up to 3 degrees. The bending was then worsened along the subsequent process steps causing mechanical failure after fin reveal where up to 7-8 of bending angles were observed. After having studied the influence of the key process steps, we can report a path to mitigate this phenomenon. Finally, we propose a simple mechanical analysis to validate quantitatively the root cause and extrapolate the mechanical robustness of this system for further scaling nodes where fin pitch is reduced.

In this study, we explored the key properties and functionalities of plasma enhanced atomic layer deposition (PEALD) SiNx films, synthesized using different deposition temperatures (500–550 °C) and plasma conditions (lower and higher), both on 300 mm blanket Si and on several integrated 3D topology substrates, at the thicknesses relevant for diverse nanoscale applications. Our study shows that with an increase of temperature (500–550 °C), a small reduction in HF wet etch rate (1.1–0.69 nm/min), and H content (9.6% vs 7.4%) was observed. When using higher plasmas, significant improvements in blanket properties were observed. The films were denser (2.95 g/cm3), exhibited lower H content (2.4%), showed better etch rates (0.39 and 0.44 nm/s for HF and CF4 based), and SiNx grew without any nucleation delay on alternative Si1−xGex channel surfaces. The vertical and lateral conformality was found to be similar and appears not to be impacted with the plasma conditions. Extensive steam oxidation barrier studies performed at the sidewalls of different aspect ratio lines showed the PEALD SiNx liner scaling potentiality down to 1 nm when deposited using higher plasma. In addition, the outer gate and inner spacer properties were found to be superior (with lower loses) for higher plasma films when subjected to several dry etch, strips, and H3PO4 chemistries. The outstanding conformality (90%–95% on aspect ratios ≤10:1) combined with excellent high end material properties in the ultrathin regimes (1–10 nm) corroborate the virtue of PEALD SiNx toward integration in scaled down and advanced nanoelectronics device manufacturing.

The impact of channel length (LG) scaling on the PBTI is studied on High-k First (HKF) Replacement Metal Gate (RMG) planar devices. The threshold voltage shift (ΔVT) due to PBTI is measured for long to short devices for different halo dose implants. It is shown that for a constant overdrive voltage (VOV), the ΔVT due to PBTI decreases as LG scales. The rate of ΔVT decrease with LG is sensitive to halo dose variation and it reduces as halo dose increases. The underlying mechanism of ΔVT vs. LG roll-off is explained by measuring the gate current density on NMOS transistors and capacitors, and TCAD simulations.

This work reports on charging damage induced by gate antennae in high- $\kappa $ (HK) Replacement Metal Gate (RMG) technology for the HK-first and HK-last integration flows, comparing plate and comb layouts. For the HK-first devices, a significant degradation of the Gate Induced Drain Leakage (GIDL) occurs for both types of antennae, which is analyzed in terms of activation energy and corresponding trap characteristics. The degradation of the HK-last transistors is attributed to top oxide deposition which causes a different degradation pattern. In this case, charging damage leads to a degradation of the gate leakage which correlates with the “aspect ratio” of the antenna. These differences are explained and analyzed based on the plasma characteristics.

Buried power rail (BPR) is a key scaling booster for CMOS extension beyond the 5-nm node. This work demonstrates, for the first time, the integration of tungsten (W) BPR lines with Si finFETs. BPR technology requires insertion of metal in the front-end-of-line (FEOL) stack. This poses risks of stack deformation and device degradation due to metal-induced stress and contamination. To assess the stack deformation, we demonstrate W-BPR lines which can withstand source/drain activation anneal at 1000 °C, 1.5 s, without adversely impacting the stack morphology. To address the contamination risk, we demonstrate a BPR process module with controlled W recess and void-free dielectric plug formation which keeps the W-line fully encapsulated during downstream FEOL processing. Suitable choice of BPR metal such as W with high melting point which does not diffuse into dielectrics also minimizes the risk of contamination. To assess the device degradation, simulations are carried out showing negligible stress transfer from BPR to the channel. This is experimentally validated when no systematic difference in the dc characteristics of CMOS without BPR versus those in close proximity to floating W-BPR lines is observed. Additionally, the resistance of the recessed W-BPR line is measured ~120 Ω/μm for critical dimension (CD) ~32 nm and height ~122 nm. The recessed W-BPR interface with Ru 3-nm TiN liner via contact can withstand more than 1000 h of electromigration (EM) stress at 6.6 MA/cm2 and 330 °C, making Ru a candidate for via metallization to achieve low resistance contact strategy to BPR.

A new methodology is demonstrated to assess the impact of fabrication inherent process variability on 14-nm fin field effect transistor (FinFET) device performance. A model of a FinFET device was built using virtual device fabrication and testing. The model was subsequently calibrated on Design of Experiment corner case data that had been collected on a limited number of processed fab wafers. We then performed 400 virtual experiments comprising seven sources of process variation. Using this virtual fabrication technique, we were able to identify a minimum gate-to-source/drain spacer thickness for a high-temperature post-EPI rapid thermal anneal (RTA) anneal process that avoided device subthreshold slope penalties. The model allowed us to determine the optimal Si recess depth target and process window prior to source/drain epitaxy. We obtained these results by reviewing device performance as a function of statistical process sensitivity and highlighting key process parameters requiring variation control. These experiments would have been impractical to perform in an actual fab, due to the time, cost, and equipment requirements of running 400 fab-based process variation experiments for each process parameter. This methodology can be used to avoid wafer-based testing during early technology development.

In this work, different charging mechanisms occurring during processing of the high-κ first gate stack of planar NMOS devices are disentangled by comparing various shapes of gate-on-field antennae. Based on different electrical measurements, the distinct electrical signatures of the charging damage related to these mechanisms are shown. Finally, a qualitative explanation is proposed in terms of oxide traps/charges and plasma bias polarity to account for this difference.

The continuous down scaling of the dimensions for the logic devices has imposed to carefully track the pattern collapse issue when cleaning after FIN etch. Showing the limitations of the hot IPA drying technique toward scaled FIN dimensions, a cleaning using a surface modification drying technique has been proposed and successfully implemented. It is also discussed the use of some post treatment solutions to remove the grafted layer used to modify the FIN surface while preserving the integrity of the FIN structures.

As CMOS scaling proceeds with sub-10 nm nodes, new architectures and materials are implemented to continue increasing performances at constant footprint. Strained and stacked channels and 3D-integrated devices have for instance been introduced for this purpose. A common requirement for these new technologies is a strict limitation in thermal budgets to preserve the integrity of devices already present on the chips. We present our latest developments on low-temperature epitaxial growth processes, ranging from channel to source/drain applications for a variety of devices and describe options to address the upcoming challenges.

Microelectronic devices enable the continuous improvement in mobile data exchange and mobile communication. This exciting technological progress has been achieved by transistor scaling, resulting in an increased performance for lower energy consumption and cost. As CMOS device scaling proceeds, the number of epitaxial growth steps in device fabrication schemes increases. Examples are SiGe or Ge as high mobility channel materials [1-3], SiGe/Si or SiGe/Ge multi-layers to define nanowires in lateral Gate All Around (GAA) devices [3-5], and Source/Drain (S/D) stressor layers which also allow to reduce the S/D contact resistance [3,6-8]. In this contribution we will describe the characteristics of the epitaxial growth schemes as used for Fin and Gate-All-Around (GAA) devices. For Si- and SiGe-channel GAA devices, strained SiGe/Si multi-layers, which are used to define lateral nanowires, can be grown with conventional precursors (SiH4 or SiCl2H2 and GeH4). The compositional gradient is sufficiently steep to allow efficient wire release by selective SiGe or Si removal [2,5,9]. In case of Ge GAA, epitaxial growth of Ge-rich SiGe/Ge on SiGe Strain Relaxed Buffers is more challenging. Extremely low process temperatures are required to avoid strain relaxation. These layers need to be grown with higher order precursors, since conventional precursors become ineffective [4]. The epitaxial growth of ultra-thin Si layers on (strained) Ge fins or lateral nanowires used to passivate Ge surfaces in the high-k gate module has been discussed at the ECS Fall meeting of 2017 [10] and will not be covered in this presentation. A major challenge is to increase the active doping concentration in epitaxial S/D layers. Current scaling of gate and fin pitch reduces contact area and the contact resistance becomes a key contributor to device parasitics [7,11]. In addition, monolithic 3D integration, requires to reduce the thermal budget of the complete epitaxial growth scheme (including pre-epi surface cleaning). For Si:P, we demonstrated that P doping activation can be increased by post-epi anneals (>1e21 cm-3) without major strain loss [8]. Nearly similar active doping concentrations (up to 8e20 cm-3) are obtained by using Si3H8 instead of SiCl2H2 and low growth temperatures without the need for a post epi thermal treatment. For SiGe:B, we obtained similar active boron concentrations using conventional precursors [12,13]. Because of the low boron solubility in Ge, it is more challenging to fabricate S/D Ge pMOS contacts with the right lattice constant (to act as a stressor) and with a sufficiently high active doping concentration. Effort is ongoing to increase the active boron concentration by moving the growth process further away from equilibrium. This is done at low growth temperatures by either using Ge2H6 as high-order precursor or by assessing new materials such as GeSn. On blanket wafers, higher active doping concentrations have been reported but it is extremely challenging to translate this into a selective growth process without Sn precipitation. This triggered the research community to assess alternative dopants. For Ge, the Ga doping solubility is significantly higher than that of B. Epitaxial growth schemes are preferred above ion implantation as the latter one requires an unwanted high thermal budget for doping activation and on patterned wafers it does not allow conformal doping profiles. First Ge:Ga layers with a resistivity below 0.4 mΩ.cm have been grown without any detectable C incorporation. In addition, Ga + B co-doping enables to reduce the resistivity of SiGe:B:Ga, which confirms the potential of Ga as an add-on. Acknowledgements The imec core CMOS program members, European Commission, the TAKEMI5 ECSEL project, local authorities and the imec pilot line are acknowledged for their support. Air Liquide Advanced Materials is acknowledged for providing advanced precursor gases. References [1] C. H. Lee et al., IEDM 2017, p. 820. [2] H. Mertens et al., VLSI 2015, p. 142. [3] L. Witters et al., IEEE Trans. On Electr. Dev. 64 (4), 4587 (2017). [4] A. Hikavyy et al., Mater Sci Semicond Process 70, 24 (2017). [5] H. Mertens et al., VLSI 2016, p. 158. [6] K.D. Weeks et al., Thin Solid Films 520, 3158 (2012). [7] E. Rosseel et al., ECS Trans. 75 (8), 347 (2016). [8] A. Hikavyy et al., ECS Trans., 60 (1), 497 (2014). [9] K. Wostyn et al. ECS Trans. 69 (8), 147 (2015) [10] R. Loo et al., ECS J. of Solid State Sci. Techn. 7 (2), P66 (2018). [11] P. Raghavan et al., Proc. IEEE Cust. Integr. Circuits Conf., p. 1 (2015). [12] A. Hikavyy et al. ECS Trans., 64 (6) 831 (2014), [13] A. Hikavyy et al., Thin Solid Films 602, 77 (2016).

In this paper, we model fin pitch walk based on a process flow simulation using the Coventor SEMulator3D virtual platform. A taper angle of the tin core is introduced into the model to provide good agreement with silicon data. The impact on various Self-Aligned Quadruple Patterning process steps is assessed. Etch sensitivity to pattern density is reproduced in the model and provides insight on the effect of fin height variability.