In this paper, we present a Design-Technology Co-Optimization (DTCO) methodology of a heterogeneous 2.5D system that aims at integrating a passive interposer with HPC chiplets. The interposer comprises 3D high-density decoupling capacitors with the power delivery network (PDN) of the HPC chiplets. The proposed methodology is based on the discretization of the interposer into unit-cells and uses spatially distributed SPICE modeling to achieve voltage drop optimization, thus improving the performance of the chiplets at system level, in iterative loop processes. Using Electromagnetic (EM) simulation for unit-cells, incorporating boundary conditions that can be customized, we found out that neighboring cells play a significant role in the voltage drop seen inside the unit-cell as a result of resistive and inductive distributed parasitic interconnects. Consequently, these adjacent cells were incorporated into the EM simulation set-up for accurate power integrity analysis at system level.

In recent piezoelectric DC-DC converters (PRC) demonstrations, notable performance is achieved with discrete transistors and high input voltages (>10's V). However, there's a gap in designs integrating all power switches on a single chip and targeting lower voltages. This study explores the influence of circuit technologies, switching frequency, and input voltage on PRC performance in the context of a fully integrated power stage. Unlike existing literature, our analysis factors in driving loss to define the frequency limit of the PRC. To achieve an optimal balance between efficiency and current density, we propose a systematic method for sizing the power stage and the piezoelectric resonator. Comparative results reveal that a power stage in classical CMOS technologies achieves efficiencies over 90% at frequencies in the 10's MHz range, including driving loss, at 0.3 A/cm(2). Emerging GaN IC technologies demonstrate a 5x reduction in total power loss compared to Si-based counterparts. Lastly, a comparison of the three main PRC topologies unveils distinct design spaces, each offering unique advantages.

This work describes two designed and fabricated circuits for power device integration in 650 V e-mode GaN-on-Si technology and gives their main measured characteristics. The first circuit is a voltage reference designed to compensate process, voltage and temperature (PVT). The advantage of this circuit over state-of-the-art circuits is its performance of regulation, low current consumption and surface required (only 100 µm x 60 µm in the first prototype built). The second circuit is a zero-crossing current detector that is also designed to be insensitive to process variations. It exhibits stable static characteristics and bandwidth observed in simulation of more than 10 MHz. The convenience of this circuit is its simplicity because no differential amplifier is used to make a comparison. Both circuits are designed to be integrated with power transistors in GaN technology to be used in ACF or other topologies capable of switching at 650 V.

Monolithic integration of GaN power transistors is considered as the ultimate implementation. Indeed, it minimizes the parasitic inductances while reducing the die area. However, the shared silicon substrate is at the origin of parasitic effects which result in higher losses. Although recent works highlight some solutions, they lead to processes that are more complex. As an alternative, this study proposes to use a printed circuit board embedded die package to compete with the monolithic solution. Thermal and parasitic aspects are investigated. This paper demonstrates that this level of integration is well suited for applications under 1kW without complex backside process.

This paper explores the possibility to achieve an integrated circuit with GaN transistors for power electronics applications. GaN provides only N type transistors. Power transistors are presented with the layout and standard useful characterization results at wafer level and chip level. A gate driver is shown, layout and performance, it demonstrates the difficulty to obtain fast rising edges using only type N type transistors. Another key function for integrated circuit is the level shifter, here a circuit capable of shifting a logic level up above the common rail of an inverter leg switching up to 400V at 1MHz. Finally, an integrated inverter leg is presented and tested switching 400V at 1MHz under 3A.

Isolated current and voltage sensors are key components in hybrid or electrical vehicles. For such applications, a low power 16-channel current sensor with 12-bit resolution at 3kS/s per channel and 1.5kV isolation has been developed. It is based on the cointegration of spin-valve Giant MagnetoResistance (GMR) thin-film technology and CMOS technology in one ASIC. Current measurements have been performed with less than 3.5% peak-to-peak non-linearity over a 1 to 20mA current range. The signal BW ranges from DC to 500Hz, and the readout circuit power consumption is only 182μW per channel.

A wide range of current-sensing techniques has been developed to satisfy various electrical and electronics applications requirements. In high-voltage applications, the main issue is the electrical isolation with accurate measurement at low signal levels. Isolated shunt technology is an attractive and versatile solution for current sensing. Electrical isolated products usually need a power supply at both low and high voltage sides. An original topology that needs only one power supply at the secondary (low voltage) side is reported. In this paper, we introduce an implementation of an integrated shunt current-measurement microsystem based on a 6 kV isolated micro-transformer. This work finds its applications in many domains such as hybrid or electric vehicle battery monitoring or motor control, system building automation or smart grids, where small size and low cost are required.

This paper reports on the design and the manufacturing of an integrated DCDC converter, which respects the specificity of sensor node network: compactness, high efficiency in acquisition and transmission modes, and compatibility with miniature Lithium batteries. A novel integrated circuit (ASIC) has been designed and manufactured to provide regulated Voltage to the sensor node from miniaturized, thin film Lithium batteries. Then, a 3D integration technique has been used to integrate this ASIC in a 3 layers stack with high efficiency passives components, mixing the wafer level technologies from two different research institutions. Electrical results have demonstrated the feasibility of this integrated system and experiments have shown significant improvements in the case of oscillations in regulated voltage. However, stability of this output voltage toward the input voltage has still to be improved.

In this paper, we propose an on-chip dc-dc buck converter for fine-grain dynamic voltage scaling (DVS) on a multi-power domain SoC. The proposed circuit converts from the I/O voltage to the required core operating voltage. This regulator is equipped with the programmable output buffer and the switching signal modulator according to the module operating condition. The proposed converter is fabricated with a 65-nm standard CMOS logic process within the area of 5 bonding pads. The maximum power efficiency is over 88%, and the leakage current in the deep stand-by mode is measured only 19 nA.

This paper proposes an on-chip dc-dc converter for a fine grain IP-level DVS. Linear and switching regulators are compared considering this particular application. The chosen buck converter operates with the I/O power supply and uses two discrete devices, a capacitor and an inductor. A test design adaptable to the various operation modes of a logic block is described. Simulation results of the proposed dc-dc converter demonstrate that the maximum power efficiency is over 90% and the leakage current is reduced down to 84 nA.

This paper discusses a local power supply unit designed for fine grain dynamic voltage scaling (DVS) in a multi-power domain SoC. The proposed power supply unit is fully compatible with an I/O library and adaptable to various logic module power needs. It delivers the module operating voltage, from 1.2 V to 0.6 V, according to predefined operating power modes and is equipped with the module power gating. The designed circuit requires five-I/O-pad pitch area in a 65-nm technology. The first test chip demonstrates that the maximum power efficiency is over 87% and the measured current consumption in stand-by mode is only 19 nA regardless of the connected module.

A harvesting microsystem is a heterogeneous component that is to say with at least one element none strictly electric. Several key points have to be taken into account to achieve a design of this kind of system: software-hardware partitioning, multi-physics simulation, 3D integration. This article introduces a top down methodology from specifications to layout. After a focus on specificities and needs of autonomous microsystems, the proposed methodology will be used to design an autonomous power generator unit including two micropower sources and their management IC: a RF power receiver and a IV miniature thermogenerator with a dedicated DC/DC up converter are combined with an manager and charger, and a discharge monitor to manage and store the harvested energy in an above-IC microbattery.Finally, consumption reduction by specified static and dynamic architecture and regulation between load and source will introduce the need of energy optimization algorithm in the proposed methodology.

Designing a digital IR focal plane array (IRFPA) requires fulfilling very stringent requirements in terms of power consumption, silicon area and speed. Among the various ADC architectures like successive approximation, ramp or over-sampled converters, the best choice strongly depends on the application. We believe that sigma-delta converters, in spite of their quite high power consumption, are a promising solution for high-performance and medium size FPA, e.g. 320x240. This paper presents the design of a second-order incremental sigma-delta ADC dedicated to cooled (77K) IRFPA applications. System-level simulations used to define the modulator parameters and specify its analog building blocks are presented. Circuit design of the switched-capacitor modulator and the digital decimation filter is described. The column ADC including the filter has been implemented in a standard 0.35μm CMOS process on the basis of a 25μm pitch and lead to a total length of 3200μm. Test chips including a single ADC have been manufactured end of 2006. The first measurement results, at 77K, are presented along with perspectives and future developments. They demonstrate the following performance: 81dB Signal-to-Noise Ratio (SNR), 13 bits Effective Number Of Bits (ENOB) and 270μW power consumption at 17kSamples/s rate.

In this paper we show the latest achievements of HgCdTe-based infrared bispectral focal plane arrays (FPAs) at LETI infrared laboratory. We present and compare the two different pixel architectures that are studied now in our laboratory, named “NPN” and “pseudo-planar”. With these two technologies, a wide range of system applications in dual-band detection can be covered. Advantages of both architectures will be pointed out. We also review performances obtained with these different architectures. The first one has been studied for several years in our laboratory, and we review results obtained on FPAs of size 256 × 256 pixels on a 25 μm pitch, in the MWIR/MWIR (3 μm/5 μm) range. Very high noise equivalent temperature difference (NETD) operability is obtained, at 99.8% for the λc = 3 μm band and 98.7% for the λc = 5 μm band. The second one has been developed more recently, to address other applications that need temporal coherence as well as spatial coherence. We show detailed performances measured on pseudo-planar type FPAs of size 256 × 256 pixels on a 30 μm pitch, in the MWIR/LWIR (5 μm/9 μm) range. The results are also very promising for these prototypes, with NETD as low as 15 mK for an integration time as short as 1 ms, and good operability. The main manufacturing issues are also presented and discussed for both pixel architectures. Challenging process steps are, firstly, molecular beam epitaxy (MBE) HgCdTe heterostructure growth, on large substrates (cadmium zinc telluride) and heterosubstrates (germanium), and, secondly, detector array fabrication on a nonplanar surface. In particular, trenches or hole etching steps, photolithography and hybridization are crucial to improve uniformity, number of defects and performances. Some results of surface, structural and electrical characterizations are shown to illustrate these issues. On the basis of these results, the short-term and long-term objectives and trends for our research and development are presented, in terms of pixel pitch reduction, wavelengths, and dual-band FPA size.

The purpose of this paper is to present the latest developments in Defir (LETI / Sofradir joint laboratory) in the field of bi-color and dual band infrared focal plane arrays (FPA) made with HgCdTe.The npn structure is achieved using the Molecular Beam Epitaxy (MBE) technique, planar ion implantation, and both dry and wet etching steps. This back to back diode architecture that allows a perfect spatial coherence with a high field factor and large quantum efficiencies needs only one indium bump connection per pixel. This makes it possible to achieve small pitches (below 25 mu m) and opens the way to the fabrication of large FPAs (TV/4 to TV) with reasonable wafer sizes.In this paper we present electro optical characterizations of 256x256 prototypes fabricated in Defir operating in two MWIR bands (3.1 and 5 mu m) with a pitch of 25gm that exhibit background limited performances together with a very high operability (above 99.9%) and NEDT below 22mK for integration time of only 0.5ms. In parallel an industrial product soon available from Sofradir has been developed with a 320x256 format and with a 30 mu m pitch operating in the same bands. This product exhibits the same operability and NETD as low as 15mK for an integration time as short as I ins. Finally, last results regarding 256x256 prototypes operating in MWHZ/LWIR bands are presented, together with preliminary APD operating mode for the MWIR photodiodes of this last dual band detector.

The purpose of this paper is to present the electro-optical performances of dual-band infrared detectors operating in a fully spatially coherent mode, with a small pixel pitch. The successive steps of device fabrication are first exposed, including molecular beam epitaxy (MBE), technological processing, and readout circuit design. It is shown that very high-quality multiple layer heterostructures of HgCdTe can be grown and processed into 256×256 arrays of 25-µm pitch mesas, each mesa including two photodiodes with different cutoff wavelengths ranging in the midwave infrared (MWIR). Characterization of these focal plane arrays (FPAs) shows very good homogeneity, low defect density, and operabilities usually above 99% for both response and noise equivalent thermal difference (NETD).

CEA/LETI has been working for several years on the development of HgCdTe-based infrared dual band detectors [3]. Since 2001 CEA/LETI is also involved in a large program for the demonstration of dual band QWIP FPAs presenting large format and small pitch. This study is carried out with the QWIP team of THALES Research and Technology (TRT) in charge of QWIP design, MBE growth and GaAs processing for the detector side. As part of this program TRT investigated different quantum structures and pixel architectures for the realization of two-band FPAs for MWIR/LWIR and LWIR/LWIR applications. At the end of this study a choice of the most appropriate architecture was done. On its side, CEA/LETI designed readout circuits optimized for the selected dual-band QWIP. TRT delivered QWIP arrays and CEA/LETI proceeded to the assembly, integration and electro-optical characterization.The aim of this paper is to describe the architecture of these dual-band demonstrators and to present the first results concerning their electro-optical performances measured at 70K and 65K.

In this article, we present recent developments of the research in France at LETI infrared laboratory in the field of complex third-generation HgCdTe IRCMOS focal plane arrays (FPAs). We illustrate this with three prototypes of FPAs made at LETI, which have involved some technological improvements from the standard process today in production at Sofradir. We present, using molecular-beam epitaxy (MBE) growth, a 128 × 128 dual-band infrared (photodetector)-complementary metal oxide semiconductor (IRCMOS) with a pitch of 50 µm operating within 2–5 µm. Using the more conventional liquid-phase epitaxy (LPE) growth, we show a new generation of high-performance long linear arrays (1500 × 2; pitch, 30 µm) operating in medium-wavelength infrared (MWIR) or long-wavelength infrared (LWIR) bands based on a modular architecture of butted HgCdTe detection circuit and SiCMOS multiplexers. Finally, we present for the first time a megapixel (1000 × 1000) FPA with a pitch of 15 µm operating in the MWIR band that exhibits a very high performance and pixel operability.