This paper presents the high throughput heterogeneous integration (HI) chiplet packaging process flow and final builds that resulted in a complete computer system (processor, memory, I/O, energy harvesting power source, sensors, operating system software) on a substrate (< 1mm 2 ). This includes details of bond and assembly material set development and demonstration for entire small chip packaging integration to achieve, for example, temporary wafer bonding and debonding on extremely small die dimensions (100-250µm on a side), and to achieve reliable and high throughput system-on-a-carrier packaging with a diverse set of CMOS, GaN and GaAs chip technologies. The interchangeable compact HI system package builds include chiplet functions containing tamperproof 32 bit processor with memory, analog I/O, with flexibility in supporting on the same package substrate footprint III-V or Si optical sources and detectors, and optical energy harvesting photovoltaics.

This work advances the current understanding and performance assessment of chiplet interfaces by providing a framework for modeling and joint simulation of signal and power integrity of BoW-based die-to-die interconnects with advanced packaging technology. The study covers data rates up to 16 Gbps. This paper presents a circuit-level implementation of the BoW slice that consists of a driver on one chiplet and a receiver on another chiplet. This work compares the performance of various combinations of high-density transmission lines with different line-and-space and wirelengths. It presents configurations of the BoW data lines that have extremely low power dissipation, less than 0.2 pJ/bit at 8 and 16 Gbps.

The growth in demand for small form-factor and more capable electronic devices is driving a corresponding need for for advances in high-density interconnect technology to support high-speed, power efficient data transfer between chiplets or between systems-on-chip and memory. This paper presents, for the first time, electrical modeling and characterization results for $2-\mu \mathrm{m}$ line and space (L/S) and $1.5-\mu \mathrm{m}$ L/S signal wiring in high-density wiring layers in a panel-level organic interposer to address this need. The first part of this paper shows various high-density routing configurations $(< 5\mu\ \mathrm{m})$ formed in organic thin films, explicitly focusing on the effect on signal phase delays, crosstalk, insertion loss, and the range of characteristic impedance that fine line structures can provide; in this discussion, impedance matching to mitigate reflections is considered. To verify high-density signaling models, the second part of the paper focuses on electromagnetic simulations and hardware measurements taken at frequencies up to 20 GHz for 5.9-mm and 1.3-mm single-ended transmission lines. In addition to the agreement between measurement and simulation results for both $2-\mu \mathrm{m}$ and $1.5-\mu \mathrm{m}$ L/S configurations up to 20 GHz, this paper quantifies measured per-unit-length insertion loss of the high density wires at multiple frequencies to serve as a standard of comparison.

This paper provides the full HBM3 system interconnect signal integrity design, link budget analysis and a positive timing margin closure solution for the latest generation high density organic laminate capable of line widths and spaces of $1.5\mu \mathrm{m}$ . Also analyzed is the high density organic packaging scalability that includes inter-layer misregistration and dielectric thickness variations.

This paper discusses deign considerations for on-chip antennas on high resistivity silicon. For proper design of these antennas, the bulk silicon needs to be divided into three sublayers, namely, inversion, depletion and remaining bulk, with different effective resistivity to account for silicon surface charge.

The focus of this work encompasses signal integrity (SI) design and analysis in hybrid integration of the latest generation of High Bandwidth Memory (HBM2E) onto the latest generation high density Organic Package now capable of 1.5um line and space interconnects. In this paper, for the first time, we design and analyze the whole system HBM2E link budget components on latest generation high density Organic Package where the methodology details all the interconnect signal uncertainties.

This paper discusses some design and implementation issues related to GaN micro-LED (μLED) incorporated into the heterogeneous packaging of IBM’s smart and secure sensor platform. For cost effective μLEDs, the sapphire substrate needs to be singulated reliably and with minimum kerf perimeter, be ultra-clean and smooth to allow back side emission without scattering, and high yielding front side flip chip bonding with 20μm C4s on 40μm pitch. The GaN μLEDs are design for low voltage/low power operation with an emission area of 20μm × 20μm with critical current density of ~10nA/μm2. Power and downlink data is delivered to the system via optical energy harvesting by on-silicon carrier photovoltaics and communication photodiode, respectively. Optical amplitude modulated uplink communication by heterogeneous packaging of the GaN μLED with a 14nm CMOS smart chip will be detailed and demonstrated in presentation.

Advancement in microelectronics technology enables autonomous edge computing platforms the size of a dust mote. In article number 2004573, Ning Li and co-workers show that dust-sized photovoltaic cells on a Si substrate can be integrated using a wafer-level-packaging process with other chiplets to achieve high efficiency and high power density. This advancement unlocks the potential of large-scale manufacturing of these compact integrated systems with high performance and low cost.

Blockchain technology can increase visibility in supply-chain transactions and lead to more accurate tracing of goods as well as provide evidence of whether a product is authentic or not. A shared, distributed ledger or blockchain alone, however, does not guarantee correct and trustworthy supply-chain traceability. We argue that blockchain technology (and any other digital traceability solution) must be enhanced with methods to "anchor" physical objects into information technology, Internet-of-Things and blockchain systems. Only when trust from the digital domain is extended to the physical domain can the movement of goods be accurately traced (e.g., for callbacks and provenance) and product authenticity determined. In this paper, we introduce the concept of crypto anchors, propose a classification and system architecture, and give implementation examples for different use cases and industries.

Conventional light-emitting diodes (LEDs) face an efficiency droop at low current due to non-radiative recombination overtaking radiative recombination at low carrier density. To overcome this universal problem, we develop LEDs with high efficiency at ultralow current and voltage, using a novel quantum well design and high-quality interfaces to suppress non-radiative recombination and enhance radiative recombination. The device exhibits close to unity internal quantum efficiency at a low current density of <1 × 10 −4 A cm −2 , more than three orders of magnitude lower than conventional LEDs. The LED bias voltage is reduced to ~30% below the photon voltage ( hν / q ). Wireless communication is demonstrated at these low-power conditions, which enables new applications in smart dust and sensor networks 1 – 6 , low-cost block chain and authentication 7 – 9 , medical applications 10 , 11 and wherever high efficiency at low power is needed. New phenomena such as high-efficiency electroluminescent cooling becomes possible as the LED unity internal quantum efficiency extends to smaller voltage and current.

Wearables that continuously acquire medically relevant parameters can reduce duration of hospitalizations and derive treatment optimizations for individual patients thus improving the quality of medical treatments. We demonstrate an architecture that includes wearables, edge and cloud computing to provide optimal user interaction and analytics of multi-parameter wearable data to accomplish this goal. We also explore the trade-offs of on-wearable processing versus raw data transmission and the use of commercial location monitors to acquire indoor location data.

Wearables that continuously acquire vital and other medically relevant parameters facilitate treatment optimizations for individual patients and reduce the duration of hospitalizations - thus improving the patients' quality of life. To accomplish this, we demonstrate a scalable architecture that connects wearables through a hub to the cloud, combines edge and cloud computing to provide optimal user interaction, and allows analytics on multi-stream data from those connected devices.

Monolithic CMOS photonics seeks to minimize total transceiver cost by simplifying packaging, design and test. Here we examine 25 Gb/s applications in the context of integrated transistor performance and demonstrate a 4λ×25 Gb/s reference design.

We report on the design, fabrication, packaging and characterization of a 4-channel semiconductor optical amplifier (SOA) flip-chip mounted on a photonic carrier. Significant loss occurs across high radix silicon photonic switching platforms due to multiple switching stages, waveguide crossings and I/O coupling elements. To overcome these losses, we propose the hybrid integration of a III-V SOA onto a photonic switch carrier to realize a gain neutral switch. Custom four channel cleaved facet SOA variants were designed with unique mounting structures for precise vertical alignment. A photonic carrier test site was designed with unique SiN waveguide coupling structures, vertical reference stops, a trench with metal lines and AuSn solder bumps for device bonding. Individual SOAs were attached to photonic carriers using a precision flip-chip bonder. All assemblies exhibited good bond strength and no line-line shorts were observed. The SOA and assembled test sites were characterized in the 1.5- 1.6 μm wavelength range. A net SOA/photonic carrier optical gain of greater than 10 dB was observed.

Grating couplers are proposed for polarization-independent coupling of light between a single-mode fiber and a 220-nm-thick channel waveguide on silicon-on-insulator. The grating couplers have nonuniform grating periods that are composed of the intersection or union of a set of two near-optimal TE- and TM-grating periods. The proposed grating couplers have a coupling efficiency greater than 20% and polarization dependent loss (PDL) lower than 0.5 dB within 3-dB bandwidth in design. For the evaluation of the design concept, a fabricated intersection grating coupler has the PDL of less than 0.8 dB within the wavelength range of 1540 to 1560 nm, and the coupling efficiency is ∼18%.

A manufacturable platform of CMOS, RF and opto-electronic devices fully PDK enabled to demonstrate a 4×25 Gb/s reference design is presented. With self-aligned fiber attach, this technology enables low-cost O-band data-com transceivers. In addition, this technology can offer enhanced performance and yield in hybrid-assembly for applications at 25 Gbaud and beyond.

The design and demonstration of photonic grating couplers with improved efficiencies monolithically integrated in IBM's 7RF silicon-on-insulator (SoI) complementary metal–oxide–semiconductor (CMOS) technology offering are reported. The grating couplers are fabricated using two standard layers available in 7RF SoI CMOS, where focusing circular grating structures and a small-footprint tapered slab are fabricated on the poly-silicon and crystalline-silicon (c-Si) layers, respectively. The coupling efficiencies for 1.3- and 1.55- $\mu{\rm m}$ grating couplers are measured to be ${-}{\rm 2.8}$ and ${-}{\rm 3.8}~{\rm dB}$ , respectively. These results are at least $2\times$ more efficient than the best previously reported grating couplers in this technology, which were fabricated using c-Si layers only. Furthermore, the devices exhibit 1-dB bandwidths of ${\sim}{40}$ and 52 nm for 1.3 and ${\rm 1.55}~\mu{\rm m}$ , respectively.