We present a strictly nonblocking $4$ × $4$ electrooptic silicon photonic switch fabric with on-chip gain. The switch integrates 12 Mach-Zehnder cells in a 3-stage topology equipped with fast electrooptic phase shifters, and thermooptic phase trimmers. To compensate for the losses of the fabric, a 4-channel GaInAsP/InP semiconductor optical amplifier array is flip-chip attached into an etched cavity in the silicon photonic chip with butt-coupled waveguide interfaces. The chip is wirebonded to a CMOS driver that provides push-pull drive to each elementary Mach-Zehnder cell. We demonstrate an optical switch assembly with net neutral insertion loss in the C-band together with nanosecond-scale reconfiguration time.

We describe the advancements made on the automated assembly of a highly integrated 8x8 photonic switch. This switch is designed for maximum efficiency but requires proximity of optical and electrical interconnects and a well-conceived thermal solution. These constraints command innovative packaging approaches. A "fiber-last" assembly process was selected, which leverages a flip-chip joining solution to preserve the sensitive optical interfaces of the photonic circuit. A multi-fiber attach process relying on fiber self-alignment in V-grooves is used for the optical interface through which the high-speed signals are routed. It is also demonstrated that a performant optical switch engine can be constructed using standard low-cost electronic assembly principles.

We demonstrate a fully-packaged digitally programmable 8x8 strictly nonblocking electrooptic silicon photonics switch module. We measured fiber-to-fiber loss between 7.5 and 10.5 dB, crosstalk < -30 dB, and reconfiguration time < 10 ns.

This work presents the first fully packaged silicon photonics 8x8 switch with monolithically integrated electrical control circuits in 90nm SOI CMOS. The switch is a strictly non-blocking network built from 2x1 and 2x2 Mach-Zehnder switches (MZSs). 180 DACs tune the MZSs and 112 ADCs measure optical power across the network for feedback control. Digital interfaces provide low-speed tuning/monitoring and high- speed switching controls. 5.6ns optical switching is achieved with thermo-optically tuned crosstalk <-33.5dB.

We report on efforts to develop a high speed, low cost, low energy chip scale optical module for co-packaging on a first-level organic substrate for HPC and Data Center applications.

We present a silicon photonic switch assembly integrating a nonblocking 4×4 Mach-Zehnder switch and a flip-chipped SOA array. The switch provides close to net-neutral-loss in the full C-band for all states and shows nanosecond-scale reconfiguration time.

We report on efforts to develop optical and electrically packaged photonic switch modules in monolithically integrated CMOS technology and to interface these modules with an FPGA-based control plane facilitating reconfiguration in tens of nanoseconds.

This paper presents an analysis on the loop dynamics of the digital clock and data recovery (CDR) circuits and the design details of a non-return to zero optical receiver (RX) in a 14-nm bulk CMOS finFET technology with high jitter tolerance (JTOL) performance, which is designed based on the analysis. The digital CDR logic is designed full custom in order to keep it running at a quarter rate clock of 15 GHz at 60-Gb/s sampling speed to minimize the CDR loop latency. The RX is characterized in a vertical cavity surface emitting laser-based link recovering a 7-bit pseudo-random bit sequence bit pattern at 60 Gb/s with a JTOL corner frequency of around 80 MHz while maintaining an energy efficiency of 1.9 pJ/bit.

The rapid increase of bandwidth requirements between processors in high-end servers motivates the integration of optical interconnects on the first-level processor package [1]. In this perspective, additional bandwidth density can be achieved by integrating optical transceivers directly into the processor die. Optically enabled CPUs can provide energy-efficient, low-latency interconnects over long distances (>10m) in future data-centers. Integrated photonic interconnect technology will require sensitive and low-power receiver (RX) circuits that operate at high data rates.

Optical switch networks based on silicon photonics can provide high bandwidth, low latency, low power, and low cost interconnect fabrics for datacenter, cloud, and high-performance computing by eliminating the pin-constrained electronic switches and the multiple electrical-optical conversions necessary in traditional networks. Silicon photonics is also compatible with wavelength division multiplexing (WDM) allowing simultaneous routing of large bandwidth data streams. Adoption of photonic switches requires scaling to large port counts compared to current 4x4 and 8x8 demonstrations. For example, a 64-port switch implemented using thirty-two 4x4 and four 16x16 switches will be limited by losses in numerous subcomponents, including optical couplers, waveguide propagation losses, waveguide crossings, and phase shifters. To enable viable optical-link-loss budgets requires incorporation of optical gain in addition to improved efficiency in all subcomponents. We have developed a silicon photonic switch platform with integrated gain based on a carrier with active photonics. Optical switches are monolithically integrated into photonic carrier while semiconductor optical amplifiers (SOAs) and CMOS drive ICs are flip-chip attached. We demonstrated non-blocking 4x4 Si photonic switches with < 3-dB on-chip loss and < -20 dB crosstalk with about 4ns switching time. Photonic carriers and 4-channel SOA arrays were co-designed with custom precision packaging features enabling flip-chip bonding with high accuracy. The photonic carrier incorporates low-loss SiN waveguides with inverse taper structures for efficient coupling to/from the SOA arrays and off-carrier coupling. Photonic carriers with integrated 4-channel SOA arrays were fabricated achieving over 10 dB gain and demonstrating error-free 4x25-Gb/s WDM links for all 4 channels.

A 64-Gb/s high-sensitivity non-return to zero receiver (RX) data-path is demonstrated in the 14-nm-bulk FinFET CMOS technology. To achieve high sensitivity, the RX incorporates a transimpedance amplifier whose gain and bandwidth are co-optimized with a 1-tap decision feedback equalization (DFE). The DFE, which operates at quarter-rate, features a look-ahead speculation to relax DFE timing to 4 unit-interval. The analog front end includes a transadmittance transimpedance inductorless variable gain amplifier, resulting in a low power and compact front end. The RX, wirebonded to a discrete GaAs photodiode, achieves an energy efficiency of 1.4 pJ/bit and −5-dBm optical modulation amplitude while recovering PRBS-7 data (bit-error-rate $<10^{-12}$ ) modulated by a VCSEL driver with a 2-tap feed forward equalization (FFE) (main + precursor) over 7 m of graded-index 50/125- $\mu \text{m}$ multimode fiber. The measured sensitivities at 56 and 32 Gb/s are −9- and −13-dBm optical modulation amplitude, respectively.

We demonstrate for the first time a 4×50Gb/s NRZ SWDM VCSEL link over 50m OM4 multimode fiber achieving error free operation (BER<;1E-12). Transmission of 4×44Gb/s SWDM over 100m OM4 fiber with error free is also presented.

Hybrid integration of a 4 -- channel semiconductor optical amplifier array onto a silicon photonic carrier with integrated SiN waveguides has been demonstrated. Custom packaging features are designed into the silicon photonic carrier, including efficient waveguide optical coupling structures, an etched trench with metal lines and AuSn solder pads for SOA integration, and vertical reference stops for precise SOA vertical alignment. Custom 1550-nm SOA arrays with 4 channels at 250-μm pitch providing > 20 dB gain were fabricated. The SOAs incorporate packaging structures designed for flip-chip assembly to the photonic carrier. A 1-μm assembly target was established from optical coupling tolerance measurements. A bonding process was developed to assemble SOA/photonic carrier modules with good bond strength and accurate alignment. Fiber coupling to the assembled modules demonstrated > 10 dB fiber-to-fiber gain over 60-nm bandwidth centered at 1550 nm for all 4 SOA channels. Gain ripple in the optical spectrum was significantly reduced with the incorporation on index-matching optical underfill. High-speed studies showed each SOA channel supports error-free 4-wavelength 25 Gb/s WDM links.

We demonstrate a 1530 nm VCSEL that can operate error-free without DSP or FEC to 56 Gb/s. At 50 Gb/s, error-free operation is attained up to 2 km of SMF. A two-tap FFE driver is used to precompensate the response of the VCSEL. The optical spectrum of the VCSEL under equalization at 50 Gb/s is analyzed and the chirp properties are reported. The low latency of FEC-free NRZ and the distance of 2 km makes these technology suitable for optical links in both high performance computing and large data centers.

We report on an 850nm VCSEL based link operating error free to 71 Gb/s using an NRZ modulation format. This optical link uses custom transmitter and receiver ICs with 2-tap Feed Forward Equalization implemented in 130nm BiCMOS and GaAs based VCSELs and photodiodes. This paper covers new aspects of the circuits and packaging.

We built a 4-channel photonic carrier with input/output SiN waveguides and a flip-chip-attached SOA array, incorporating end-to-end reflection-management and mode-matching. All channels demonstrate fiber-to-fiber gain of >10dB and support error-free 4-λ × 25-Gb/s WDM links.

We report on the design, fabrication, packaging and characterization of a 4-channel semiconductor optical amplifier (SOA) flip-chip mounted on a photonic carrier. Significant loss occurs across high radix silicon photonic switching platforms due to multiple switching stages, waveguide crossings and I/O coupling elements. To overcome these losses, we propose the hybrid integration of a III-V SOA onto a photonic switch carrier to realize a gain neutral switch. Custom four channel cleaved facet SOA variants were designed with unique mounting structures for precise vertical alignment. A photonic carrier test site was designed with unique SiN waveguide coupling structures, vertical reference stops, a trench with metal lines and AuSn solder bumps for device bonding. Individual SOAs were attached to photonic carriers using a precision flip-chip bonder. All assemblies exhibited good bond strength and no line-line shorts were observed. The SOA and assembled test sites were characterized in the 1.5- 1.6 μm wavelength range. A net SOA/photonic carrier optical gain of greater than 10 dB was observed.

We report error free (BER < 10(-12)) operation of a directly non-return-to-zero modulated 850-nm vertical cavity surface-emitting laser (VCSEL) link operating to 71 Gb/s. This is the highest error free modulation rate for a directly modulated laser of any type. The optical link consists of a 130-nm BiCMOS driver IC with two-tap feed-forward equalization, a wide bandwidth 850-nm VCSEL, a surface illuminated GaAs PIN photodiode, and a 130-nm BiCMOS receiver IC.