In recent years, there have been significant advancements in electronic device technology. However, these devices remain vulnerable to Single-Event Effects (SEEs), caused by the interaction of cosmic rays with sensitive regions, potentially leading to processing errors. Thus, it is interesting to investigate the correlation between cosmic ray events and the likelihood of processing errors, particularly concerning the interactions between specific particles and the sensitive areas of the devices. This work presents a study using the Geant4 tool to simulate the interaction of cosmic rays with FET devices and their potentially associated effects. Simulations involve hitting particles such as protons, alpha particles, positive and negative pions, as well as positive and negative muons. These are injected with energies ranging from 0.5 MeV to 100 TeV and at various angles of incidence. Simulations demonstrate that alpha particles generate the most electrons, which is especially relevant in outer space environments. Protons, which constitute the majority of cosmic rays, significantly affect SEEs not only in outer space and low Earth orbit but also at ground level. Although positive muons and pions have a lesser effect, they become prominent at lower altitudes, including at ground level. The angle of incidence is critical in evaluating SEEs, with planar technologies showing a higher occurrence of electron generation. In contrast, finFETs, although producing fewer electrons, exhibit a greater potential for generating bit flip currents.

Like most computer systems, a manycore can also be the target of security attacks. It is essential to ensure the security of the NoC since all information travels through its channels, and any interference in the traffic of messages can reflect on the entire chip, causing communication problems. Among the possible attacks on NoC, Denial of Service (DoS) attacks are the most cited in the literature. The state of the art shows a lack of work that can detect such attacks through learning techniques. On the other hand, these techniques are widely explored in computer network security via an Intrusion Detection System (IDS). In this context, the main goal of this document is to present the progress of a work that explores an IDS technique using machine learning and temporal series for detecting DoS attacks in NoC-based manycore systems. To fulfill this goal, it is necessary to extract traffic data from a manycore NoC and execute the learning techniques in the extracted data. However, while low-level platforms offer precision and slow execution, high-level platforms offer higher speed and data incompatible with reality. Therefore, a platform is being developed using the OVP tool, which has a higher level of abstraction. To solve the low precision problem, the developed platform will have its data validated with a low-level platform.

Convolutional neural networks (CNNs) have become a standard technology in numerous industrial Internet of Things (IoT) applications and sectors, such as automotive and aerospace. Recent advancements in hardware and software (e.g., application programming interface (API)/libraries) components have enabled the efficient execution of multithreaded CNN models on edge devices. As the complexity and adoption of CNNs in safety-critical systems continue to grow, ensuring their resilience becomes key and increasingly challenging. In this context, this work promotes two original contributions: 1) the proposal of a multithreaded implementation of MobileNet, which achieves a 2.67x speedup and an energy reduction of 16% with four worker threads, and 2) the first soft error reliability assessment of a multithreaded CNN model running in a multicore processor under high-energy and thermal neutron radiation flux. Results from the radiation campaigns, with more than 31k runs, suggest that multithreaded executions can increase the occurrence of critical faults by up to 5x . Results also show a greater number of events during the thermal neutron campaign, and some input images are significantly more robust against silent data corruption (SDC) events.

Sparse linear algebra is essential in many domains due to reduced computation and efficient memory usage. However, the irregularity of sparse data poses challenges for conventional software and hardware. While specialized accelerators offer performance gains, they lack general-purpose flexibility and rely on processor communication, creating bottlenecks. This work addresses these issues by proposing a tiling strategy to improve vector register usage and extending the RISC-V Vector (RVV) ISA with a custom merge instruction. Experiments using the gem5 simulator show that the tiled vector version achieved speedups of up to 1.30x (95% sparsity) and 1.72x (65%). In contrast, the version with merge instructions reached up to 1.81x and 6.04x, respectively, over a baseline implementation.

The landscape of Unmanned Aerial Vehicles (UAVs) or drones technology and their applications is increasingly evolving across various sectors. UAV s are subject to radiation-induced single event upset (SEUs); assessing their vulnerability is thus vital to avoid possible catastrophic events. This paper's original contribution is to assess the SEU vulnerability of four UAV control algorithms running in a resource-constrained micropro-cessor. Results suggest the PID for attitude and height control has the best relative trade-off between SEU vulnerability, memory-saving, performance, and power efficiency. Results also show that a self-tuning PID controller using fuzzy theory presented fewer silent data corruption (SDCs) than all other algorithms.

The presence of Unmanned Surface Vehicles (USVs) is increasingly frequent on lakes and water reservoirs, performing tasks such as monitoring water quality or delivering goods across the water. However, the emergence of such autonomous vessels raises concerns in terms of safety for people sharing the same environment and the risk of collisions with fixed structures and floating bodies, including other vessels. Therefore, the detection of obstacles and its reliable operation become primary in USVs. This work explores the effects caused by neutron radiation on an object detection algorithm tailored for USVs. Results report 77 silent data corruption (SDC)-induced failures, showing that radiation-induced soft errors contribute to missed and false detection of respectively existing and non-existent objects. Furthermore, results suggest that object detection algorithms running with the multi-core strategy ( FITSDC rate of 34.3 at sea level and 308.6 at Lake Titicaca) exhibit a 16.4% greater resilience to SDCs compared to the single-core strategy.

There is a growing incorporation of unmanned aerial vehicles (UAVs) within remote and urban environments due to their versatility and ability to access hard-to-reach and/or congested places. UAVs offer low-cost solutions for many applications, including healthcare (e.g., medical supplies delivery) and surveillance during public events, protests, or emergencies (e.g., nuclear accident). However, drone utilisation in urban areas often relies on strict regulations to ensure safe and responsible operation. UAVs are subject to radiation-induced soft errors, and identifying the most vulnerable software and hardware components to radiation exposure is a advisable task, which is difficult to undertake. An essential task to UAVs correct operation is attitude estimation. This paper assesses the soft error reliability of three attitude estimation algorithms running on two resource-constrained microprocessors under neutron radiation. Results suggest that the extended Kalman filter (EKF) algorithm provides the best mean work to failure result for critical fault events, which is about 3× more than the indirect Kalman filter (IKF) and 1.5× more w.r.t. the novel quaternion Kalman filter algorithm (NQKF).

This paper promotes a novel semi-automated compiler-based technique that allocates CNN weights and bias to SRAM parity checking areas. Radiation results suggest that it is possible to reduce critical SDC events by up to 90%.

The proliferation of sensitive information and data processing in the Internet of Things edge and end devices is accelerating at a rapid pace. As a result, ensuring security becomes increasingly crucial. Although encryption is essential, edge devices often cannot accommodate large overheads. This study assesses the efficiency of ten lightweight cryptography (LWC) algorithms by comparing their power consumption, performance, and memory footprints in ARM Cortex architectures. The goal is to guide designers working with LWC and ARM processor architectures. The LWC algorithms, along with the baseline Advanced Encryption Standard (AES), are implemented and executed on ARM Cortex-M processors, intended for edge devices. Results reveal trade-offs associated with cipher properties and the inherent architectural resources of each processing device.

The evolution of robotic systems supporting coprocessing can limit a multitude of uses and their effective deployment in real life. Although computing time still accounts for a non-negligible part of system performance, communication latency is increasingly relevant, as the growing use of heterogeneous co-processing in complex systems makes communication among elements a performance bottleneck. To undertake this coming challenge, this work evaluates the efficiency of a set of relevant communication protocols supported in ROS-based systems with co-processing. Results show UDP is the best choice for the transport layer, especially for high-performance systems. TCP-based communication can nonetheless play a role in low-end co-processing robotics.

Soft error resilience has become an essential design metric in electronic computing systems as advanced technology nodes have become less robust to high-charged particle effects. Designers, therefore, should be able to assess this metric considering several software stack components running on top of commercial processors, early in the design phase. With this in mind, researchers are using virtual platform (VP) frameworks to assess this metric due to their flexibility and high simulation performance. In this regard, herein, this goal is achieved by analysing the soft error consistency of a just-in-time fault injection simulator (OVPsim-FIM) against fault injection campaigns conducted with event-driven simulators (i.e. more realistic and accurate platforms) considering single and multicore processor architectures. Reference single-core fault injection campaigns are performed on RTL descriptions of Arm Cortex-M0 and M3 processors, while gem5 simulator is used to multicore Arm Cortex-A9 scenarios. Campaigns consider different open-source and commercial compilers as well as real software stacks including FreeRTOS/Linux kernels and 52 applications. Results show that OVPsim-FIM is more than 1000× faster than cycle-accurate simulators and up to 312× faster than event-driven simulators, while preserving the soft error analysis accuracy (i.e. mismatch below to 10%) for single and multicore processors.

The use of pre-designed and pre-verified hardware modules, also called IP cores, is an important part of the effort to design and implement complex systems. However, many aspects of IP core manipulation are still to be developed. This paper presents an approach to solveproblems related to the dynamic interconnection of hard IP cores. The approach targets system-on-a-chip designs build in a single FPGA device. The paper proposes a communication interface that allows IP cores replacement during the FPGA normal operation. The same interface also allows the communication among distinct IP cores to take place.

The management of many-core systems is evolving to meet multiple objectives simultaneously. The Software-Defined Networking (SDN) has benefits explored in recent works that point it as a candidate to address this requirement at the communication level, at the same time that promotes management flexibility and reduced hardware complexity. Most of the research in SDN for many-cores assumes a centralized SDN (C-SDN) Controller and single-objective management. This work proposes multi-objective management based on a distributed SDN (D-SDN) architecture (SELF-SDN). The management is selfadaptive, addressing QoS and fault-tolerance simultaneously at the communication level. Experiments targeting QoS show that SELF-SDN provides a reduced amount of latency misses (-67%) and fast reaction time (-49.6%) to recover the QoS constraints compared to a C-SDN approach. Fault-tolerance experiments highlight the simplicity of the SDN paradigm to recover from faults in the NoC, not requiring additional hardware. Results related to multi-objective management demonstrate the fast reaction time of SELF-SDN to recover the communication latency faced to QoS loss and faults, reducing, on average, in 43% the reaction time compared to a C-SDN approach.

New technology nodes enable the integration of billions of transistors in a small silicon area by replicating identical structures, resulting in many-core systems. However, power density may limit the amount of energy the system can consume. A many-core at its maximum performance may lead to safe temperature violations and, consequently, result in reliability issues. Dynamic Thermal Management (DTM) techniques proposals guarantee that many-core systems run at good performance without compromising reliability. In this paper, we review recent DTM works, discussing their limitations, and propose new heuristics for thermal-aware application mapping and migration, using a hardware accelerator that enables temperature monitoring on systems with a large number of processing elements. Results show that using straightforward heuristics, with reactive actions based on runtime temperature monitoring, reduce the peak temperature in high workload scenarios (6.8%), and improve thermal distribution significantly on a large (8×8) many-core system.

For almost a decade now, Network on Chip (NoC) concepts have evolved to provide an interesting alternative to more traditional intrachip communication architectures (e.g. shared busses) for the design of complex Systems on Chip (SoCs). A considerable number of NoC proposals are available, focusing on different sets of optimization aspects, related to specific classes of applications. Each such application employs a NoC as part of its underlying implementation infrastructure. Many of the mentioned optimization aspects target results such as Quality of Service (QoS) achievement and/or power consumption reduction. On the other hand, the use of NoCs brings about the solution of new design problems, such to the choice of synchronization method to employ between NoC routers and application modules mapping. Although the availability of NoC structures is already rather ample, some design choices are at base of many, if not most, NoC proposals. These include the use of wormhole packet switching and virtual channels. This work pledges against this practice. It discusses trade-offs of using circuit or packet switching, arguing in favor the use of the former with fixed size packets (cells). Quantitative data supports the argumentation. Also, the work proposes and justifies replacing the use of virtual channels by replicated channels, based on the abundance of wires in current and expected deep sub-micron technologies. Finally, the work proposes a transmission method coupling the use of session layer structures to circuit switching to better support application implementation. The main reported result is the availability of a router with reduced latency and area, a communication architecture adapted for high-performance applications.

In many-cores based on Network-on-Chip (NoC), several applications execute simultaneously, sharing computation, communication and memory resources. This resource sharing leads to security and trust problems. Hardware Trojans (HTs) may steal sensitive information, degrade system performance, and in extreme cases, induce physical damages. Methods available in the literature to prevent attacks include firewalls, denial-of-service detection, dedicated routing algorithms, cryptography, task migration, and secure zones. The goal of this paper is to add an HT in an NoC, able to execute three types of attacks: packet duplication, block applications, and misrouting. The paper qualitatively evaluates the attacks' effect against methods available in the literature, and its effects showed in an NoC-based many-core. The resulting system is an open-source NoC-based many-core for researchers to evaluate new methods against HT attacks.

Side channel attacks (SCA) are known to be efficient techniques to retrieve secret data. In this context, this paper concerns the evaluation of the robustness of secure triple track logic (STTL) against power and electromagnetic analyses on FPGA devices. More precisely, it aims at demonstrating that the basic concepts behind STTL are valid in general and particularly for FPGAs. Also, the paper shows that this new logic may provide interesting design guidelines to get circuits that are resistant to differential power analysis (DPA) attacks which and also more robust against differential electromagnetic attacks (DEMA).

This work presents a framework for heterogeneous many-core SoCs generation, which comprises a flexible EDA (Electronic Design Automation) framework and a many-core model for heterogeneous SoCs. The framework together with the many-core model supports the integration of processors, network interfaces, routers, and peripherals. The hardware model is cycleaccurate, with a SystemC model to speed up simulation time and a VHDL model enabling prototyping in FPGAs devices. The framework provides a rich set of graphical debugging tools enabling an easy and intuitive understanding of computation and communication events happening at runtime. The coupled integration of the platform model to the EDA framework makes the many-core well suited to be employed in research and teaching. As case-study, we provide an evaluations addressing the many-core generation, simulation, and debugging.

This work presents Memphis, which comprises a flexible EDA framework and a many-core model for heterogeneous SoCs. The framework, together with the many-core model supports the integration of processors, network interfaces, routers, and peripherals. A set of tools enable a decoupled generation and compilation of the hardware, operating systems, and applications. The hardware model is cycle-accurate, with a SystemC model to speed up simulation time and a VHDL model enabling prototyping in FPGAs devices. The framework provides a rich set of graphical debugging tools enabling an easy and intuitive understanding of computation and communication events happening at runtime. The coupled integration of the platform model to the EDA framework makes Memphis well suited to be employed in research and teaching. As case studies, we provide a set of evaluations addressing the many-core generation, simulation, and debugging. Different applications sets were employed, enabling to characterize the computation and communication performance of the many-core, as well as, evaluate an AES encryption application performance according to different levels of parallelism.