Graphene presents interesting opportunities but also faces unique challenges for applications in nanoelectronics. As a gapless semiconductor, with an inert surface that is difficult to grow high quality gate dielectrics on, or chemically dope, it can be challenging to make graphene field effect transistors (GFETs) with low leakage currents, low interface state densities, and low source/drain series resistance. However, the Dirac cone bandstructure with high a Fermi velocity enables high frequency GFETs with ambipolar characteristics which can be used, for instance, in simple frequency doublers. Beyond-CMOS low power device ideas include single particle 2D-2D interlayer tunnel FETs (ITFETs), or more esoteric many-body tunneling devices such as the Bilayer Pseudospin FET (BiSFET).

(Fig. l(b)) p-i-n device structure analyzed here.Thep-type source doping ismaintained at1020 cm-3, while then-type drain doping isallowed tovaryfrom1020 to1018 cm-3. TheSiO2gateoxide thickness is 2nm,thebodythickness is20nmforbothgeometries, andthechannel length is100nm.Fig. 2(a) shows anexample ofthedrain current (ID) measured vsthegate-source bias (VG) fortheDG device withadrain doping of1020 cm-3, andatdrain biasVD=1V.Thedevice posses asmall subthreshold slope combined withambipolar characteristics, whichstemfromband-to-band (BTB)tunneling carrier injection atthe drain-channel [VG O, Fig.2(c)] junction. A keyresult ofour simulations isshowninFig. 3(a), wheretheID-VG characteristics fortheDG geometry areexamined for three different drain doping levels. Thedata showsthat byreducing thedrain doping from1020 to1018 cm-3, theambipolar characteristic forVG<Oiscompletely suppressed. Thephysical interpretation ofthis result isprovided inFig. 3(b) whereweshowtheenergy bands vsposition along thedevice structure. Theelectric field atthedrain-channel junction isreduced whenthedrain doping level islowered, which translates into avirtual suppression oftheBTBtunneling atthis junction. Thedata ofFig. 4(a) showsacomparison oftheID-VGcharacteristics forthree device geometries, namely single, double andgate-all-around geometry. Thisdatashowthat theGAA device provides an ON-state current morethananorder ofmagnitude larger thantheplanar counterparts. Theresult canbe understood byexamining theenergy banddiagram ofFig. 4(b), whichshowsthat theelectric field atthe source-channel junction ishighest fortheGAA geometry. TheBTB tunneling ratedepends exponentially ontheelectric field, resulting inahigher tunneling current fortheGAA device geometry. Lastly, inFig. 5weshowacomparison ofthegatedelay (t), defined asr = CVDIION, vsION/IOFF ratio forVD= 0.3V, 0.5Vand1V.HereC isthegeometric capacitance ofthedevice, andIONandIOFF represent theON-state andOFF-state currents. Thisdataset isgenerated using simulated ID-VG data asin Fig. 4(a) forthethree different values ofVD,andthendefining anoperating gatevoltage range equal to thevalue ofVD.Thedata ofFig. 5substantiate thefindings ofFig. 4whichshowthat theGAA device geometry hasthesmallest gatedelay atagiven ION/IOFF ratio. Finally, we notethatwhileexactdevice design parameters (e.g. doping profile atthe source/drain contacts, gateoverlap, channel doping) ortheexact band-to-band tunneling mechanism will certainly impact quantitatively ourdevice performance analysis, thequalitative conclusions (1)and(2) drawnhereareexpected toholdindependent ofthese details.

The direct tunneling current has been calculated for the first time from an inverted p-substrate through different gate dielectrics by numerically solving Schrodinger's equation and allowing for wave function penetration into the gate dielectric stack. The numerical solution adopts a first-order perturbation approach to calculate the lifetime of the quasi-bound states. This approach has been verified to be valid even for extremely thin dielectrics (0.5 nm). The WKB solution agrees well with the tunneling currents predicted by this technique. For the same effective oxide thickness (EOT), the direct tunneling current decreases with increasing dielectric constant, as expected. However, in order to take full advantage of using high-k dielectrics as gate insulators, the interfacial oxide must be eliminated. We also present for the first time the C-V curves obtained assuming that the wave function penetrates into the oxide.