The observation of room temperature sub-60 mV/dec subthreshold slope (SS) in MOSFETs with ferroelectric (FE) layers in the gate stacks or in series with the gate has attracted much attention. Recently, we modeled this effect in the framework of a FE polarization switching model. However, there is a large amount of literature attributing this effect to a stabilization of quasi-static (QS) negative capacitance (NC) in the FE. The technological implications of a stabilized non-switching (NS) QSNC model vs a FE switching model are vastly different; the latter precluding applications to sub-60 mV/dec SS scaled CMOS due to speed limitations and power dissipated in switching. In this letter, we provide a thorough analysis assessing the foundations of models of QSNC, identifying which specific assumptions (ansatz) may be unlikely or unphysical, and analyzing their applicability. We show that it is not reasonable to expect QSNC for two separate capacitors connected in series (with a metal plate between dielectric (DE) and FE layers). We propose a model clarifying under which conditions a QS "apparent NC" for a FE layer in a FE-DE bi-layer stack may be observed, quantifying the requirements of strong interface polarization coupling in addition to capacitance matching. In this regime, our model suggests the FE layer does not behave as a NC layer, simply, the coupling leads to both the DE and FE behaving as high-k DE with similar permittivities. This may be useful for scaled EOT devices but does not lead to sub-60 mV/dec SS.

Graphene presents interesting opportunities but also faces unique challenges for applications in nanoelectronics. As a gapless semiconductor, with an inert surface that is difficult to grow high quality gate dielectrics on, or chemically dope, it can be challenging to make graphene field effect transistors (GFETs) with low leakage currents, low interface state densities, and low source/drain series resistance. However, the Dirac cone bandstructure with high a Fermi velocity enables high frequency GFETs with ambipolar characteristics which can be used, for instance, in simple frequency doublers. Beyond-CMOS low power device ideas include single particle 2D-2D interlayer tunnel FETs (ITFETs), or more esoteric many-body tunneling devices such as the Bilayer Pseudospin FET (BiSFET).

In this paper, bilayer pseudospin FET (BiSFET) is fabricated and tested for the condensate using Coulomb drag measurements in the double layer graphene system. The basic BiSFET structure can also be used as 2D-2D single particle tunnel FET, and the single particle h-h and e-e 2D-2D tunnel FETs, which is graphene's single-atom thickness could lead to more ideal interlayer tunneling characteristics provided the layers can be aligned. Single particle tunneling current calculations have been performed which show NDR characteristics, reminiscent of the BiSFET, albeit with higher operating powers.

Electronic devices have been explored in the past based on resonant single-electron CB (conduction band) to CB tunneling between parallel quasi-two dimensional (2D) quantum wells within III-V heterostructures and their accompanying negative differential resistance (NDR) [1]. Such devices are attractive for high speed electronics, and digital logic circuits also have been demonstrated using a combination of conventional and such NDR FETs [2]. For two graphene layers separated by a tunnel barrier, we recently proposed the ultra-low-voltage Bilayer pseudoSpin FET (BiSFET) which would employ enhanced nonresonant VB (valence band) to CB tunneling, with a nevertheless very sharp NDR characteristic based on a predicted room-temperature many-body superfluid state [3]. However, NDR due to resonant single-particle CB-to-CB or VB-to-VB tunneling may also be achievable in such a structure. Furthermore, the atomically near-perfect 2D nature of the component graphene layers and the conduction/valence band symmetry may offer advantages over III-Vs. Here, we model the I-V characteristics due to single-particle tunneling in such a structure, Fig. 1, using a perturbative tunneling Hamiltonian approach [4,5], and deviations from this simple theory using atomistic tight-binding nonequilibrium Green's function (NEGF) simulation.

The Bilayer pseudo-spin Field Effect Transistor (BiSET) has been proposed as one means of taking advantage of possible room temperature superfluidity in two graphene layers separated by a thin dielectric. In principle, the switching energy per device could be on the scale of 10 zJ, over two orders of magnitude below estimates for "end-of the roadmap" CMOS transistors. However, achieving both the goal of room temperature superfluidity and harnessing it for low-power switching pose substantial challenges, both theoretical and experimental. In this work we review the basic graphene superfluidity and BiSFET concepts, our current understanding―and limits to that understanding―of the requirements for condensate formation, and how these requirements could impact BiSFET design.

A new parameter extraction technique has been outlined for high-/spl kappa/ gate dielectrics that directly yields values of the dielectric capacitance C/sub di/, the accumulation layer surface potential quotient, /spl beta//sub acc/, the flat-band voltage, the surface potential /spl phi//sub s/, the dielectric voltage, the channel doping density and the interface charge density at flat-band. The parallel capacitance, C/sub p/(=C/sub sc/+C/sub it/), was found to be an exponential function of /spl phi//sub s/ in the strong accumulation regime, for seven different high-/spl kappa/ gate dielectrics. The slope of the experimental lnC/sub p/(/spl phi//sub s/) plot, i.e., |/spl beta//sub acc/|, was found to depend strongly on the physical properties of the high-/spl kappa/ dielectric, i.e., was inversely proportional to [(/spl phi//sub b/m/sup *//m)/sup 1/2/K/C/sub di/], where /spl phi//sub b/ is the band offset, and m/sup */ is the effective tunneling mass. Extraction of /spl beta//sub acc/ represented an experimental carrier confinement index for the accumulation layer and an experimental gate-dielectric direct-tunneling current index. /spl beta//sub acc/ may also be an effective tool for monitoring the effects of post-deposition annealing/processing.