The Innovative Micro Electro Mechanical Systems (I-MEMS) device was developed to reduce the power consumption of next-generation electronic devices. I-MEMS devices eliminate standby power when used as a power gating device. In logic circuit applications, I-MEMS devices provide for extremely low power consumption and remain robust during high temperature operation. I-MEMS devices are very reliable and can operate at current CMOS digital voltage (1V). This paper will review current MOSFET and MEMS technologies, analyze problems in conventional MEMS, and provide solutions for these problems.

High-frequency performance of graphene field-effect transistors (GFETs) has been limited largely by parasitic resistances, including contact resistance (RC) and access resistance (RA). Measurement of short-channel (500 nm) GFETs with short (200 nm) spin-on-doped source/drain access regions reveals negligible change in transit frequency (fT) after doping, as compared to ∼23% fT improvement for similarly sized undoped GFETs measured at low temperature, underscoring the impact of RC on high-frequency performance. DC measurements of undoped/doped short and long-channel GFETs highlight the increasing impact of RA for larger GFETs. Additionally, parasitic capacitances were minimized by device fabrication using graphene transferred onto low-capacitance quartz substrates.

We report measurement of fast transient charging effects (FTCE) in enhancement-mode n-channel GaAs, InP, and In0.53Ga0.47As field-effect transistors (FETs) using Al2O3 as the gate dielectric. The FTCE data reveal superior drive current and enhanced threshold voltage stability for In0.53Ga0.47As FETs. We further report charge pumping measurements for In0.53Ga0.47As transistors, revealing that the majority of interface traps are donor traps, as well as an increased trap density within the Al2O3 bulk. Such data, together with FTCE data, reveal that drain current degradation observed during pulsed I-V measurements is predominantly due to slow oxide traps, underscoring their significance within III-V/high-κ metal-oxide-semiconductor FETs.

Graphene presents interesting opportunities but also faces unique challenges for applications in nanoelectronics. As a gapless semiconductor, with an inert surface that is difficult to grow high quality gate dielectrics on, or chemically dope, it can be challenging to make graphene field effect transistors (GFETs) with low leakage currents, low interface state densities, and low source/drain series resistance. However, the Dirac cone bandstructure with high a Fermi velocity enables high frequency GFETs with ambipolar characteristics which can be used, for instance, in simple frequency doublers. Beyond-CMOS low power device ideas include single particle 2D-2D interlayer tunnel FETs (ITFETs), or more esoteric many-body tunneling devices such as the Bilayer Pseudospin FET (BiSFET).

The graphene field-effect transistor has generated attention in recent years for its potential for fast electronics, with theoretical transit frequencies in the THz range, and fabricated devices operating at hundreds of GHz. Previously published models are based on numerical iteration or neglect the equilibrium quantum capacitance, leading to reduced accuracy around the Dirac point. We have derived a compact, physicsbased closed-form equation for drain-source current that can be implemented in a circuit level simulator. This model demonstrates strong agreement with both DC and RF measurements, as well as linear and non-linear circuits. The model also enables simulation of circuits to enable design of topologies that take advantage of the unique properties of the graphene transistor. The model also affords parameter variation analyses to quantify the adverse effects of non-idealities such as contact resistance. Finally, we have developed a quantum capacitance limited model to benchmark the performance of realistic devices against the ideal quantum capacitance limit, and elucidate the effects of oxide scaling.

Graphene presents interesting opportunities but also faces unique challenges for applications in nanoelectronics. As a gapless semiconductor, with an inert surface that is difficult to grow high quality gate dielectrics on, or chemically dope, it can be challenging to make graphene field effect transistors (GFETs) with low leakage currents, low interface state densities, and low source/drain series resistance. However, the Dirac cone bandstructure with high a Fermi velocity enables high frequency GFETs with ambipolar characteristics which can be used, for instance, in simple frequency doublers. Beyond-CMOS low power device ideas include single particle 2D-2D interlayer tunnel FETs (ITFETs), or more esoteric many-body tunneling devices such as the Bilayer Pseudospin FET (BiSFET).

We report a 500nm graphene field-effect transistor operating at the Dirac point for frequency doubling with maximum output power of −23dBm and a record bandwidth of 3GHz, 2× higher than the state-of-the-art. The experimental device exceeds its ft and fmax by about 50%. Contact resistance degrades the performance of the experimental GFET. In the limit of negligible non-idealities and maximum gate capacitance, the conversion gain approaches lossless frequency doubling. The record performance of the graphene doubler is enabled by the growth of high-quality graphene affording carrier mobilities as high as 5000cm2/V-s and 2200cm2/V-s on smooth quartz and flexible substrates respectively.

The exceptional electronic properties of graphene field-effect transistors (GFETs) make them a promlsmg replacement for conventional Si CMOS transistors for high frequency analog applications. Radio frequency GFETs with intrinsic cut-off frequencies as high as 300GHz have been reported, with theoretically predicted THz frequencies only being limited by fabrication challenges. A major factor responsible for degradation of GFET performance is high series resistance of the access regions between the source/drain contacts and the top-gated graphene channel, which reduces maximum possible drive currents. A back-gate bias can be used to modulate this resistance, but this approach does not provide for independent control of mUltiple GFETs on the same substrate and for GFETs on insulating substrates. GFETs with self-aligned gates overcome this problem by reducing the access region resistance, but their fabrication is not straightforward. Here, we propose a simple scheme of improving GFET performance by reducing the source/drain access resistance using self-aligned charge-transfer doping. A novel and controllable way of "spin-on-doping" of the access regions with chemical dopants is demonstrated.

We demonstrate a 500-nm graphene frequency doubler with a record 3-GHz bandwidth, exceeding the device transit frequency by 50%, a previously unobserved result in graphene, indicating that graphene multiplier devices might be useful beyond their transit frequency. The maximum conversion gain of graphene ambipolar frequency doublers is determined to approach a near lossless value in the quantum capacitance limit. In addition, the experimental performance of graphene transistor frequency detectors is demonstrated, showing responsivity of 25.2 μA/μW. The high-frequency performance of these gigahertz devices is enabled by top-gate device fabrication using synthesized graphene transferred onto low capacitance, atomically smooth quartz substrates, affording carrier mobilities as high as 5000 cm 2 /V ·s.

We report a method of fabricating self-aligned, top-gated graphene field-effect transistors (GFETs) employing polyethyleneimine spin-on-doped source/drain access regions, resulting in a 2X reduction of access resistance and a 2.5X improvement in device electrical characteristics, over undoped devices. The GFETs on Si/SiO2 substrates have high carrier mobilities of up to 6300 cm2/Vs. Self-aligned spin-on-doping is applicable to GFETs on arbitrary substrates, as demonstrated by a 3X enhancement in performance for GFETs on insulating quartz substrates, which are better suited for radio frequency applications.

We demonstrate the synthesis of large-area graphene on Co, a complementary metal-oxide-semiconductor (CMOS)-compatible metal, using acetylene (C(2)H(2)) as a precursor in a chemical vapor deposition (CVD)-based method. Cobalt films were deposited on SiO(2)/Si, and the influence of Co film thickness on monolayer graphene growth was studied, based on the solubility of C in Co. The surface area coverage of monolayer graphene was observed to increase with decreasing Co film thickness. A thorough Raman spectroscopic analysis reveals that graphene films, grown on an optimized Co film thickness, are principally composed of monolayer graphene. Transport properties of monolayer graphene films were investigated by fabrication of back-gated graphene field-effect transistors (GFETs), which exhibited high hole and electron mobility of ∼1600 cm(2)/V s and ∼1000 cm(2)/V s, respectively, and a low trap density of ∼1.2 × 10(11) cm(-2).

Graphene nanoelectronics have made significant progress over the past five years particularly in material synthesis, device physics, and circuit applications. The high achievable mobilities at room temperature coupled with its high linearity (or invariant-transconductance) [1], and transit frequencies that exceed conventional solid-state transistors (see Fig. 1) make it ideally suited for GHz and THz analog electronics [2]. However, there are several challenges that need to be addressed for graphene to be a next-generation technology. In this light, we report significant experimental and theoretical progress to address these challenges in three essential areas namely wafer-scale graphene synthesis, compact device modeling, and GHz analog circuits.

There has been great interest in methods for the synthesis of high-quality, large-area graphene films, as required for practical applications in the electronics industry. In particular, recent developments in chemical vapor deposition (CVD) methods have shown a promising approach to grow large-area graphene on metal substrates by catalyzed CVD growth. Reports of CVD growth on Cu and Ni are common; however, there have been few efforts to grow graphene on Co, and attempts to grow graphene on Co/SiO2/Si resulted in very small domains of predominantly multilayer graphene that were not suitable for transistor fabrication. Unlike Ni, Co is attractive due to the low lattice mismatch (<; 2%) between graphene and the Co (0001) surface, and Co exhibits greater compatibility with Si than Cu, which is a deep trap in Si and a fast diffuser. Here we have demonstrated graphene field-effect transistors (GFETs) fabricated using large-area monolayer graphene grown by catalyzed CVD on Co films.