Rapid thermal processing chemical vapor deposition (RTP-CVD) has received considerable attention because of its ability to reduce many of the processing problems associated with thermal exposure in conventional chemical vapor deposition, while still retaining the ability to grow high quality epitaxial layers. In this paper, the principles of the RTP-CVD system are described, followed by results of experiments on in-situ cleaning, undoped Si epitaxy and in-situ doped Si epitaxy, and selective Si deposition using oxide masks. Our results show that RTP-CVD is capable of growing high quality, epitaxial layers with sharp, dopant transition profiles. Selective deposition was achieved without the use of HC1. We also studied the growth and characterization of GexSi1−x films for optical waveguiding.

An optimal thickness of the metal nitride (TiN) film capped by polysilicon for the MOSFET gate electrode application is investigated. Interface trap density, which depends on the TiN film thickness and transistor channel length is suggested to be controlled by mechanical stress of the metal layer after full transistor processing including high temperature annealing. Thinner TiN gate electrode was found to have lower interface trap density. Thicker TiN, however, showed better barrier properties for impurity diffusion from the polysilicon-capping layer. We found that 10nm is the optimum thickness of the ALD TiN layer for minimizing charge trapping and adequate blocking of boron penetration.

The effects of HfO2 thickness on charge trapping and mobility were investigated. The impact of fast transient electron trapping on DC measurements results in underestimating channel carrier mobility. Scaling the physical thickness of the HfO2 dielectric causes less charge trapping and higher mobility. A HfO2 -based high-k solution requires fine-tuning the thickness of the high-k film to maintain a balance between electron trapping in thicker films and increased leakage current in thinner films.

MOSFETs with high quality ultra thin (EOT/spl sim/10.3 /spl Aring/) HfO/sub 2/ gate stacks and self-aligned dual poly-Si gate are fabricated and characterized. Both n- and p-MOSFETs show good electron and hole mobility, respectively, and excellent sub-threshold swings. In addition, the HfO/sub 2/ gate stack exhibits excellent thermal stability with poly-Si gates up to 1050/spl deg/C/30 s gate activation annealing and shows excellent TDDB reliability characteristics with negligible charge trapping and SILC under high-field stressing.

Absfruct-In this paper, we demonstrate the superior diffusion barrier properties of NO-nitrided SiOn in suppressing boron penetration for p+-polysilicon gated MOS devices. Boron penetration effects have been studied in terms of flatband voltage shift, decrease in inversion capacitance (due to polysilicon depletion effect), impact on interface state density, and chargeto-breakdown. Results show that NO-nitrided SiOz, as compared to conventional thermal SiOz, exhibit much higher resistance to boron penetration, and therefore, are very attractive for surface channel PMOS technology.

The diffusion and activation of low-energy implanted B in F preamorphized Si during rapid thermal annealing has been studied. Compared with low-energy B or BF2 implant into crystalline Si, low-energy B ion implantation into F preamorphized Si allows the formation of shallow junctions with reduced junction depth and increased B activation. F preamorphization suppresses the B transient enhanced diffusion in the low B concentration region resulting in a steep dopant profile which is necessary for shallow junction formation. Secondary ion mass spectroscopy and cross-sectional transmission electron micrograph results show F accumulation near the surface and at end-of-range defects. The interaction of F with defects is believed to reduce B diffusion in the low B concentration region. Low-energy B implant into F preamorphized Si followed by rapid thermal annealing has been demonstrated as a promising process for shallow junction formation.

The electrical properties of MOS capacitors with Si-implanted SiO2 are investigated. It is demonstrated that a hysteresis effect is present in the capacitance-voltage characteristics of MOS capacitors with Si-implanted gate oxide. Both fixed charge and interface state density are observed to increase with Si-implant dose. The current conduction in these oxide films was also examined.

This brief reports the effects of post-gate processing in an O2-containing ambient (less-than-or-equal-to 40% in N2), such as the source/drain annealing, and the borophosphosilicate-glass (BPSG) densification and reflow, on the metal-oxide-semiconductor (MOS) device characteristics. Compared to devices processed in a pure N2. ambient during the BPSG reflow (and with a low O2 concentration for the source/drain anneal and the BPSG densification), it is found that devices processed in the O2-containing ambient (approximately 40% O2 in N2 during reflow) show a significantly degraded low-field breakdown characteristics (e.g., 10(2)-10(4) x higher gate leakage current) when electron injection takes place at the polycrystalline silicon (poly-Si)/SiO2 interface. Results suggest that the BPSG reflow in an O2-containing ambient might induce some positive charges near the poly-Si/SiO2 interface and results in a lowered tunneling barrier and/or an enhanced injecting electric field. However, no significant difference was observed in device reliability under F-N injection for devices processed in ambients with or without O2.

The gate oxide thickness dependence of charge-trapping properties in nanometer-range thin gate oxide prepared by rapid thermal oxidation has been studied. It is shown that the high-field stress-induced charge-trapping and interface state generation (DELTAD(it)) are strongly dependent on oxide thickness. The thinner oxide has a less charge-trapping rate and DELTAD(it). In addition, the thickness dependence of DELTAD(it) is found to be a function of stress time. The detrapping behaviors of trapped charges are also thickness dependent; the thicker oxides (8-10 nm) show a significant hole detrapping whereas thinner oxides (6 nm) exhibit an electron detrapping during the off-stress periods.

This letter discusses the reliability characteristics of metal-oxide-semiconductor capacitors with chemical-vapor-deposited Ta2O5 gate dielectric films. To be compatible with the conventional polycrystalline Si-gate process, SiO2 or Si3N4 film was deposited on Ta2O5 as the top dielectric layer. It is found that under high-field stress, interface state generation is enhanced with the presence of the top dielectric layers, probably due to the anode-field increase caused by the positive-charge buildup in the stacked dielectrics capacitors. The significant positive-charge build-up in capacitors with top dielectrics is believed to be due to the hole-injection-barrier from Ta2O5 to SiO2 or Si3N4 and/or damage creation in the Ta2O5 films.

A diffusion model for ion-implanted BF2+ ions in Si for rapid thermal annealing application has been developed based on the effects of defect evolution on dopant diffusion. In addition, a simple, accurate and universal precipitation model has been developed for high dose implantation. Simulation results show excellent agreement with the experimental results.

Time-dependent dielectric breakdown under unipolar ac stress is investigated for control, nitrided, and reoxidized nitrided oxides, prepared by rapid thermal processing. All these gate dielectrics show longer time-to-breakdown under ac stress compared to constant voltage stress. Nevertheless, the extent of retardation of breakdown under ac stress is observed to be minimum for nitrided oxides and maximum for reoxidized nitrided oxides. Differences in detrapping behavior in these gate dielectrics are used to explain different improvement factors for breakdown under ac stress.

A diffusion model for ion implanted BF2 has been developed based on the diffusion and reactions of point defects and B. The simulation of enhanced diffusion under rapid thermal annealing condition has been accomplished for 2×1013–1.5×1015 cm−2 dose BF2 implant. The effects of implant damage, surface amorphization, and fluorine atoms on B diffusion have been investigated by using the as-implant defect profiles obtained from Monte Carlo simulation as the initial condition. From excellent agreement between experimental and model results, we find that chemical effects of F on B diffusion in low dose BF2 implant is minimal, and for high dose BF2 implant, the surface amorphization can be modeled by modifying the point defect profile within the amorphized region.

The diffusion of ion-implanted B during rapid thermal annealing (RTA) has been modeled by studying the reaction kinetics between eight species including boron, Si self-interstitials, and vacancies in multiple-charge states. Monte Carlo generated point-defect profiles are used to include the effects of ion-implant damage on the enhanced diffusion of B. Accurate diffusion modeling of high-dose implantation has been achieved with the addition of an extended defect model. The extended defect model describes the absorption and release of Si interstitials corresponding to extended defect formation and annealing, which give rise to the transient-enhanced diffusion of B. Good agreement between the model and experimental results for RTA of ion-implanted B at a dose range of 1×1014–2×1015 cm−2 has been obtained.

We report calculated bound-state transition energies at 77 K for symmetrically strained Si1-xGex/Si quantum wells grown on (100) Si substrates. The red shift in transition energies with bias due to the quantum-confined Stark effect is also examined. Transition energies are plotted as a function of Ge concentration, quantum-well thickness, and applied electric field. The calculations are based on phenomenological deformation potential theory and the envelope function method popularized by G. Bastard [Phys. Rev. B 24, 4714 (1981)]. The results presented here are useful for the design of Si1-xGe(x)Si optoelectronic modulators operating at 1.3 and 1.55-mu-m.

The role of extended defect evolution on the anomalous diffusion of boron during rapid thermal annealing (RTA) was studied by investigating the diffusion behavior of boron implanted into various Si substrates using secondary ion mass spectroscopy and transmission electron microscopy, i.e., predamaged wafers with low dose Si implantation, preamorphized wafers with high dose Si implantation, and single-crystal wafers without any previous implantation. Low-dose Si preimplantation reduced the channeled tail significantly in subsequent boron implantation and resulted in a larger anomalous diffusion of boron and faster annealing of extended defect during RTA compared to crystalline Si samples. Diffusion of boron implanted into preamorphized Si was found to be anomalous in nature and its magnitude was dependent upon the RTA temperature. The temperature dependence was found to be due to the difference in the density of dislocation loops formed during RTA at the original amorphous/crystalline (a/c) interface. These loops determined the effectiveness of the trapping Si interstitials diffusing from the crystalline side of the original a/c interface to the expitaxially regrown region. Anomalous diffusion of boron in the crystalline Si samples was found to be a strong function of implant dose. Diffusion displacement increased and anomalous diffusion effect lasted longer with increasing implant dose. Diffusion enhancement for longer periods of time in samples with higher implant doses was related to the formation and annealing of extended defects. At very high doses (> 2 x 10(15) cm 2), where the peak boron concentration was above the solid solubility, excess diffusion in the high boron concentration region was observed. The excess diffusion was explained in terms of segregation of boron into interstitial dislocation loops in the early stage of RTA and the subsequent annealing of these dislocation loops after the initial large anomalous tail diffusion.