This paper presents the recent mmWave and sub-THz oriented technology developments as part of RF design-technology co-optimization (DTCO) efforts in Intel 22nm FinFET process (22FFL). Several back-end-of-line (BEOL) and front-end-of-line (FEOL) improvements have been implemented for high frequency applications. In the newly developed BEOL, ExpressVia is introduced, which allows direct transistor connection to thick metal. Continuous via and 3+1 thick metal layers are enabled for design flexibility. The high performance RF transistor (RF HP) is optimized with the new BEOL and characterized at top metal. Additional process improvements in high power RF device (HyPowerFF) and varactors are also implemented. These BEOL and FEOL improvements enable high performance, innovative mmWave and sub-THz circuits and systems.

Design-technology co-optimization of Intel's first FinFET Anti-Fuse (AF) memory using 22FFL technology is reported. The nMOS based 1T1C bit cell containing TG and TnG is sized to satisfy electrical performance, process marginality, area, and reliability spec. With gate dielectric breakdown as the mechanism of bit storage, it is found that improved gate oxide integrity is beneficial to post-breakdown resistance and overall array yield. Special attention on well design, source/drain optimization, gate height targeting and array layout in the face of 3-dimentional resistor networks in FinFET can significantly modulate array health. A 2.8 k-bit AF array with baseline yield exceeding 99.9% at no added process cost with medium SA margin setting is demonstrated.

This paper presents a simulation study using a novel distributive quasi-ballistic drift diffusion (DD) TCAD model applied to low mobility unstressed and high mobility stressed scaled pMOS devices. The model is implemented in a DD simulator and used to study the gate length dependence of current drives. The new model captures the physically correct potential distribution and gives the correct drive current limit in ballistic devices for both linear current response and current saturation source-drain bias conditions. The diffusive and ballistic transport is connected using a ballistic probability, which relates to the fundamental time scale in the problem-the mean energy relaxation time. The model captures the ballistic velocity degradation from the diffusive limit at linear source-drain biases. It is shown that the DD simulation with the distributive quasi-ballistic model describes the stress ballistic drive gains at high driving field, which are missed by the existing ballistic models.

A hierarchical, model-based understanding of the key physical effects underlying stress-induced device performance gain is presented, focusing on the large gains seen for uniaxial PMOS stress conditions and the vertical stress impact on NMOS gain.