The gap between processors and main memory performance increases every year. In order to overcome this problem, cache memories are very useful. Compile-time program transformations can signi cantly improve the performance of the cache. To apply most of these transformations, the compiler requires a precise knowledge of the locality of the di erent sections of the code, both before and after being transformed. This report describes analysis techniques aiming at providing explanations to performance of a program, as far as the cache is concerned. General Reference Windows (GRWs) gives a measure of the amount of memory references that are live at any point in the execution of the program, that is, references previously loaded into the cache, and to be reused later on. Clearly if the size of the window exceeds the capacity of the cache at some point, then cache misses are due to occur at this point. GRWs can be expressed through sets of linear inequations, which one can view as polyhedra, whose number of integer points have to be computed; for this task we can use the Polylib library. The rst part of this reports explains the di culties encountered in computing the GRWs, which improvements are required from the Polylib, and how we plan to circumvent the problems. We also describe a dynamic computation of GRWs, that may be an alternative complementing the static analysis. The second part concerns Cache Miss Equations (CME) which allow to obtain an analytical and precise description of the cache memory behavior for loop-oriented codes. Describing the cache behavior by means of diophantine equations allows us to use mathematical techniques to obtain cache misses. Unfortunately, a direct solution of the CME is computationally intractable due to its NP-hard nature. In this work we present e ective techniques that exploit some properties of the particular polyhedra generated by CME. Such techniques reduce the complexity of the algorithm to solve CME from exponential to polynomial, which results in a signi cant speed-up when compared with traditional methods. We propose a fast and accurate approach to estimate the solution of the CME, which is based on the use of sampling techniques. Statistical techniques allow us to approximate the absolute miss ratio of each reference by analyzing a small subset of the iteration space. The size of the subset, and therefore the analysis time, is determined by the accuracy selected by the user. The results show that only a few seconds are required to analyze most of the SPECfp benchmarks with an error smaller than 0.01. MHAOTEU: Project No 24942

In this document, we present the experience of several partners in the process of analyzing and optimizing an application. This text describes shortly the effort of each partner performed for the MHAOTEU demo workshop held in Barcelona in September 1999. Each partner looked for an application effectively used by academic or industrial end−users (as defined in the MHAOTEU workprogramme), and attempted to optimize that application. This work should not be considered as a description of a Process for Optimizing an Application which is a planned deliverable for the third year. It should be viewed as preliminary investigations on that topic. The text is split in 5 sections, each corresponding to an application. For each application, we provide a short description of the application, performance analysis of the original program and the different steps of the analysis/optimization process.

Register constraints in ILP scheduling can be taken into account during the scheduling phase of a code. The complexity of this problem is very high. In this work, we present a new approach consisting in manipulating data dependence graphs to reduce the number of «potential» \vsa without assuming any schedule. We study theoretically the exact upper-bound of the register need for all valid schedules of a code¸: we call this limit the register saturation. It is used to build a modified data dependence graph such that any schedule of this graph will verify the register constraint- s and avoid introducing spill code. We study the case of Direct Acyclic Graphs and then we extend it to loops intended to software pipelining schedule. Experimental study shows that many DAGs and loops do not need register constraints during scheduling.

Abstract: The convergence of digital television, Internet access, gaming, and digital media capture and playback stresses the importance of high-quality and high-performance video and graphics processing. The SANDRA project, a collaboration between Philips Research and INRIA, develops a consistent and efficient system design approach for regular, real-time constrained stream processing. The project aims at providing a system template with its associated