A mechanical study of silicon interposer bow reduction, from wafer level manufacturing to large die stacking including analytical modeling, is presented in this paper. Indeed, understanding and reducing the warpage of a dissymmetrical substrate is fundamental for assembly yield and interconnects reliability. The target here is a bow less than 50 μm for a 650 mm 2 Si-interposer. This mechanical version of a power computing package demonstrator for high reliability applications integrates three top dies, whose largest is 300 mm 2 , with a 225 μm bump pitch, on a 650 mm 2 Si-interposer with a 450 μm ball pitch, itself reported on a 45 × 45 mm 2 ceramic substrate. Assembly is performed in a mass reflow oven. In this paper, the design, methodology and test vehicle process flow are firstly presented. The analytical model of the interposer bow as a function of temperature, based on the Stoney formula for small strains, is then presented. The model calibration is detailed. In this work, three levers are used to manage the bow: interposer thickness, passivation layers stress tuning, and symmetrical behavior of both faces. These actions can either shift the bow whatever the temperature, or change the bow range over temperature. Finally, the experimental results are shown. After front side manufacturing, the 725 μm thick wafer bow is reduced from 230 μm to 105 μm with optimized compressive dielectric layers. The die bow's range from ambient to assembly temperature is reduced from 50 μm to 15 μm thanks to backside processing for the 200 μm thick die. As regards the 300 μm thick die, the temperature has almost no effect on its bow which is -12 μm. Bow values after manufacturing and slopes during thermal cycles fit very well with the model developed and the assembly requirements. These results enable to fine-tune the bow and predict a very good yield and reliability for the assembly of the electrical demonstrator.

This paper presents the first 55 nm SiGe BiCMOS technology developed on a 300 mm wafer line in STMicroelectronics. The technology features Low Power (LP) and General Purpose (GP) CMOS devices and 0.45 μm2 6T-SRAM bit cell. High Speed (HS) HBT exhibits 320 GHz fT and 370 GHz fMAX associated with a CML ring oscillator gate delay τD of 2.34 ps. Transmission lines, capacitors, high-Q varactors and inductors dedicated to millimeter-wave applications are also available.

As of 45 nm node, ultralow k (ULK) materials (εr < 2.55) are widely used in microelectronic interconnects to reduce signal propagation delay. In order to get such low dielectric constant, most of these ULK are obtained using subtractive method: after co-deposition of matrix and porogen a UV cure process is used to remove labile species (porogen). During this process, porosity is created and films are densified as shrinkage increases. This paper presents an in-depth study of the UV cure process. Two kinetic models are presented to describe shrinkage rate: the nth order and the autocatalytic model. These models also used to describe photo-polymerization shrinkage-strain of dental composite, gives predictions that are in good agreement with experimental data. We find that nth-order model is best suited to describe ULK transformations during UV cure process. CHx bonds loss and carbon content can also be modeled using same kinetic model. In order to be able to build the model, initial SiOCH-CxHy film has to be over-cured to determine the maximum conversion that film can reach when submitted to extra-long cure times. Results show that such SiOCH materials have to be cured more than 250 times their nominal cure time to reach maximum shrinkage (∼50%) and a complete loss of carbon, making them looking like SiO2. When structural changes are observed at different temperature, activation energy of reactions can be determined. In this way, shrinkage reaction has an activation energy close to 1000–1100 kJ/mol and CHx bonds or carbon loss reactions have activation energy in the range of 250–400 kJ/mol, which is pretty close to C-H binding energy.

In this paper, we investigate the tendency of porous low-K dielectrics (also named Ultra Low-K, ULK) behavior to shrink when exposed to the electron beam of a scanning electron microscope. Various experimental electron beam conditions have been used for irradiating ULK thin films, and the resulting shrinkage has been measured through use of an atomic force microscope tool. We report the shrinkage to be a fast, cumulative, and dose dependent effect. Correlation of the shrinkage with incident electron beam energy loss has also been evidenced. The chemical modification of the ULK films within the interaction volume has been demonstrated, with a densification of the layer and a loss of carbon and hydrogen elements being observed.

A 32 nm node BEOL demonstrator using trench first hard mask (TFHM) architecture is realized. The dual damascene process is performed with ELK dielectric at line and via level and with an adapted metallization in order to meet ITRS specifications. ELK k=2.3 & k=2.2 are studied in a TFHM architecture in order to prove its extendibility to ELK dielectric materials.

This work analyses electromigration and dielectric lifetimes of 45 nm node CMOS interconnects. Reliability mechanisms and failure modes are discussed considering, on one hand, the interconnect materials and processes steps, and on the other hand scaling issues. Robust reliability performance meeting the required products target is actually obtained with process integration schemes used for the 45 nm node thanks to fine optimizations of Cu barriers, Cu filling, and ULK surface quality.

The introduction of SiOCH low-k dielectrics in copper interconnects associated to the reduction of the critical dimensions in advanced technology nodes is becoming a major reliability concern. The interconnect realization requires a consequent number of critical process steps [1]. Since porous low-k dielectrics are used as Inter-Metal Dielectric (IMD) each process step can be a source of degradation for the dielectric. This paper describes critical process steps influencing the low-k reliability. All the processes affecting the dielectric's interfaces are also evidenced to degrade the low-k interconnect robustness. Some process examples as the direct chemical and mechanical polishing (CMP), the slurry chemistry and the TaN/Ta barrier etching are details in this paper. Moreover, some process options are given to strongly improve low-k dielectric reliability without degradation of its electrical performances.

Des atteintes hépatiques peuvent être observées chez la femme enceinte, liées ou non à la grossesse. Cette revue a pour objectif de préciser les différentes causes d’hépatopathie au cours de la grossesse et leur prise en charge. Les hépatopathies observées chez les femmes enceintes peuvent être soit des hépatopathies aiguës gravidiques, soit des hépatopathies chroniques connues avant la grossesse ou non et dont le cours peut être modifié par la grossesse, soit enfin des hépatopathies intercurrentes qui nécessitent une prise en charge particulière pendant la grossesse. La connaissance des différentes atteintes hépatiques pouvant survenir au cours de la grossesse permettra d’assurer une prise en charge multidisciplinaire de la mère afin d’éviter la survenue de complications maternelles ou fœtales sévères.

Liver dysfunction during pregnancy can be related or not to pregnancy itself. The purpose of this review is to summarize the possible causes of liver dysfunction during pregnancy and their management. Liver dysfunction during pregnancy can be chronic or acute, independent or specific to pregnancy. Management of liver disease can be different during pregnancy. The knowledge of liver dysfunction during pregnancy is of help for a better management of the mother in order to avoid maternal and fetal mortality and morbidity. (C) 2008 Elsevier Masson SAS. Tous droits reserves.

A 32nm node BEOL integration scheme is presented with 100nm metal pitch at local and intermediate levels and 50nm via size through a M1-Via1-M2 via chain demonstrator. To meet the 32nm RC performance specifications, extreme low-k (ELK) porous SiOCH k=2.3 is introduced at line and via level using a Trench First Hard Mask dual damascene architecture. Parametrical results show functional via chains and good line resistance. Integration validation of ELK porous SiOCH k=2.3 is investigated using a multi-level metallization test vehicle in a 45nm mature generation.

Air gaps were successfully integrated in a multi level metallization interconnect stack using 65 nm design rules on 300 mm wafers. The proposed approach allows a low cost integration of localized air cavities using a sacrificial material to solve via misalignment issues. Air gap integration is shown to be mechanically robust and presents excellent electrical results with high gains on RC delays. In addition, air gaps structures tested in electromigration pass the targeted lifetime criterion. This easily scalable approach can be seriously considered either in aggressive interconnect geometries or in specific applications of existing technologies for which high electrical performance is locally required.

Deposited on a porous a-SiOC:H intermetal dielectric (IMD), a dense a-SiOC:H cap was successfully integrated in a C45 dual damascene architecture. The paper demonstrates that, stopping the CMP with around 10nm of the cap left, the IMD integrity is preserved. As a consequence, a 3.5% decrease in RC delay, a 7.3% decrease in IMD integrated k-value and an increase of the time to failure by a 100 factor are reached relative to direct CMP. The cap also allowed to achieve straight lines and to improve the lines height uniformity as if CMP stopped on the IMD.

The use of corona charge method for monitoring the electrical properties of low-k dielectrics is investigated in this paper. First, the stability and reproducibility of k measurements are demonstrated on SiO(2)-based low-k materials. As mercury probe is the reference tool for k and leakage measurements, a comparison of the dielectric constants and leakage currents between both techniques is carried out on a set of different low-k films with various dielectric constants and thicknesses. Good correlations (over 95%) were obtained for the k values and breakdown voltages on all studied layers and an 82% correlation has been obtained for leakage densities at 1 MV/cm. As a consequence, corona charge method seems to be a good alternative for mercury probe to monitor in-line back-end low-k films.

Liver dysfunction during pregnancy can be related or not to pregnancy itself. The purpose of this review is to summarize the possible causes of liver dysfunction during pregnancy and their management. Liver dysfunction during pregnancy can be chronic or acute, independent or specific to pregnancy. Management of liver disease can be different during pregnancy. The knowledge of liver dysfunction during pregnancy is of help for a better management of the mother in order to avoid maternal and fetal mortality and morbidity.

Thin TaN metallic barriers are used to prevent copper diffusion into porous low-k dielectrics such as a-SiOC:H for advanced interconnects. We investigate the detailed electronic properties of the TaN/a-SiOC:H stack. Here we combine ultraviolet and x-ray photoelectron spectroscopy to measure the chemical composition and the whole band diagram of the TaN/a-SiOC:H stack. An original interpretation based on the image-force model used for internal photoemission is suggested to explain the electric field effect induced by negative bias of a-SiOC:H. This model is used to extrapolate the unbiased electron affinity of the dielectric. TaN work function, a-SiOCH band gap, valence band maximum and electron affinity of 4.6, 7.7, 4.0, and 3.8 eV are respectively obtained. Kelvin force microscopy and spectroscopic ellipsometry confirm TaN work function and a-SiOC:H band gap measurements, respectively. From the full band diagram of the TaN/a-SiOC:H stack, an interfacial barrier height of 0.8 eV is deduced.

A new process, based on the interaction between Si and N rich gas cluster and post Cu CMP features surface, was integrated in a multi-level Cu interconnect stack using 65 nm design rules. Using the same integration scheme as stand-alone SiCN dielectric capping, excellent electrical properties were achieved when the process was implemented with a USG layer on top of a porous Ultra-Low K. Furthermore, 3x electromigration time to failure improvement was evidenced, making the approach very promising to address EM performance requirement for the most advanced technology nodes. Moreover, contrary to PE-CVD CuSiN approach, the process does not depend on Cu crystallographic orientation. Finally, when the implantation process is performed on un-capped ULK, a deep N contamination occurs. Therefore, the process must be optimized to preserve the interest of this technique for the most aggressive architectures.

Bulk and interface band diagrams are presented for porous ultra-low K SiCOH, dense SiCOH, TEOS and USG dielectrics, SiCON and SiCN etch stop layers, TaN and Ta2O5 barrier layers. These results may explain basic optical and electronic properties of advanced interconnects.

A full ULK (ultra low-k) integration using TFHM (trench first hard mask) architecture (Hinsiger et al., 2004) is demonstrated in a high density CMOS 45 nm device. 13 nm-pitch metal features have been resolved using a 193 nm immersion hyper-NA (numerical aperture) scanner and an optimized OPC (optical proximity correction) model. RC performance and yield results are presented for a fully-integrated 45 nm ULK backend. An overall speed performance enhancement of >10% has been confirmed within a microprocessor application at the 65 nm technology node when replacing Low-k dielectric (k=2.9) with ULK (k=2.5) material.