This article presents a new post-fabrication (post-fab) porous silicon (PSi) integration process adapted to standard-resistivity silicon handle substrates (10-20 Omega & sdot;cm). The process enables uniform porosification from the wafer backside through to an etch-stop layer beneath the buried oxide (BOX). This process does not involve the frontside and does not exceed 150 degrees C, ensuring full compatibility with previously fabricated devices. A metallic grid ensures homogeneous current distribution, overcoming the conductivity limitations of standard-resistivity substrates compared to the usual low resistivity substrates used for porous silicon integration. Coplanar waveguides lines are fabricated as test structures, and radio frequency measurements confirm excellent performance, including low permittivity (& varepsilon;r,eff = 4.3 at 5 GHz), high effective resistivity (>3 k Omega & sdot;cm at 5 GHz), and low harmonic distortion (H2 = -115 dBm at H1 =15 dBm). This work demonstrates that post-fab PSi integration can be achieved on CMOS-compatible standard substrates, eliminating contamination risks present with highly doped substrates and making porous silicon integration more straightforward in industrial applications.

Global interest is growing for porous silicon (PSi) as a high-performance substrate for RF applications. Despite its proven excellent properties (high effective resistivity, low effective permittivity, excellent linearity and thermal stability), its use on an industrial scale is still jeopardized due to various challenges concerning its integration. Fabrication of CMOS on PSi substrates induces mechanical stability issues. Post-fab integration of PSi was demonstrated in 2019 to overcome this problem but required highly doped Si substrate that induces contamination issues during the CMOS process. In this work, we present a new methodology to integrate PSi, under devices, after their fabrication on standard resistivity silicon substrates ($10-20 \Omega \cdot \text{cm}$). This allows obtaining a high-performance substrate featuring local high resistivity, low permittivity and excellent linearity, starting from substrates that are widely available, low-cost and without major adaptation of device fabrication.

This study presents a methodical procedure for optimizing laser desorption/ionization mass spectrometry (LDI-MS) supports using porous silicon (PSi) substrates. The approach involves the use of substituted benzyl-pyridinium salts (thermometer ions) to obtain one metric that assesses analyte fragmentation (the effective temperature of vibration). Porous silicon substrates were synthesized via electrochemical etching of p-type silicon wafers (10-20 mΩ·cm), with etching parameters adjusted to vary porosity while maintaining a layer thickness between 700 and 1200 nm. The results revealed that PSi substrates with 40-60% porosity achieved the lowest fragmentation levels. This finding was validated through the analysis of N-acetyl glucosamine, a carbohydrate, which confirmed the effective temperature trend. Further analysis involving peptides, specifically P14R and a peptide mix (Peptide Calibration Standard II, Bruker), demonstrated that the optimized PSi substrates enabled the desorption and ionization of peptides with a maximum mass at m/z 2465, corresponding to ACTH clip 1-17. These results highlight the critical role of substrate porosity in minimizing analyte fragmentation and enhancing LDI-MS performance.

The integration of porous silicon into standard-resistivity silicon substrates presents significant opportunities for enhancing the performance of RF devices while maintaining cost efficiency. Porous silicon, produced via electrochemical etching, offers low permittivity and high resistivity, making it a promising alternative to traditional high-resistivity silicon and trap-rich silicon-on-insulator substrates. This study addresses the challenges and solutions associated with post-fab porous silicon integration, focusing on standard-resistivity silicon substrates (10-20 Omegacm) to avoid contamination risks and ensure compatibility with existing processes. The impact of substrate conductivity on the heterogeneity of porosification is studied, and we demonstrate that a conductive grid deposited on the wafer backside is successfully used to evenly distribute the current and assure a uniform porosification across the entire substrate, even for wafers of large diameters. This approach, validated through finite element simulations and experiments, shows promise in ensuring uniform post-fab porosification, making the technology viable for industrial-scale wafers up to 300 mm in diameter.

This study presents a methodical procedure for optimizing laser desorption/ionization mass spectrometry (LDI-MS) supports using porous silicon (PSi) substrates. The approach involves the use of substituted benzyl-pyridinium salts (thermometer ions) to obtain one metric that assesses analyte fragmentation (the effective temperature of vibration). Porous silicon substrates were synthesized via electrochemical etching of p-type silicon wafers (10-20 mΩ⋅cm), with etching pa-rameters adjusted to vary porosity while maintaining a layer thickness between 700 and 1200 nm. The results revealed that PSi substrates with 40-60% porosity achieved the lowest fragmentation levels. This finding was validated through the analysis of N-Acetyl glucosamine, a carbohydrate, which confirmed the effective temperature trend. Further analysis involving peptides, specifically P14R and a peptide mix (Peptide Calibration Standard II, Bruker), demonstrated that the optimized PSi substrates enabled the desorption and ionization of peptides with a maximum mass at m/z 2465, corresponding to ACTH clip 1-17. These results highlight the critical role of substrate porosity in minimizing analyte fragmentation and enhancing LDI-MS performance.

DC-40 GHz single pole double throw (SPDT) microelectromechanical (MEMS) switch designed and manufactured on top of high resistivity (HR) and advanced trap-rich (TR) silicon substrates have been characterized and compared. It has been shown that the passive devices designed on TR substrate sense an effective resistivity 10 times higher than the ones designed on HR substrate. The insertion loss on an SPDT implemented on TR is 0.39 dB lower than the one on HR at 10 GHz and 0.9 dB lower at 40 GHz. Moreover, in terms of device linearity, the level of the second harmonic H2 is 20 dB lower for TR than for HR substrate, demonstrating the high efficiency of trap-rich substrate. To the authors knowledge, this is the first MEMS on TR substrate used for radio-frequency applications.

Gallium nitride (GaN) is a promising semiconductor for RF and high-power applications. However, its large-scale industrialization is hindered by several challenges, primarily the lack of cost-effective, high-performance handle substrates. Sapphire and SiC present high performances, but their use in electronic applications is limited due to their high cost. GaN-on-Si substrates are more affordable but suffer from high substrate-induced RF losses. We introduce an innovative method to mitigate the substrate losses. Porous silicon is known for decades for its high RF performance, but its integration is challenging. We performed porosification of the handle silicon substrate after the fabrication of the RF devices, from the backside, preserving the high quality of the GaN layers and the low cost of GaN-on-Si, while boosting the RF performances. We achieved harmonics H2 =-140 dBm at Pout=15 dBm, RF losses under 0.1 dB/mm at 5 GHz, and an effective resistivity higher than 8 kΩ·cm at 5 GHz.

Porous silicon (PSi) research has been active for several decades. The multiple properties and structural features of PSi have made it a promising material for a wide variety of applications, going from drug delivery to microelectronics. By removing the bulk silicon below a PSi layer and creating a membrane, a whole new set of physical and chemical characteristics as well as potential uses have been discovered. In this review, recent works on Porous silicon membranes (PSiMs) are analysed and summarised. An updated overview of the progress made in several areas is presented with the purpose of highlighting PSiM's potential. New methods for the fabrication and the integration of PSiMs have been developed, relying more and more on semiconductors microfabrication techniques. Likewise, the properties of PSiMs have been extensively studied, enabling the emergence of a multitude of PSiM-based systems. A critical analysis of the advantages and disadvantages of this material is made, with the emphasis on the integration challenges that PSiMs are facing for future industrialisation.

The surface topology of porous silicon (PSi) is a relevant parameter that decides the compatibility of such substrate with CMOS process. Using standard resistivity (1–10 Ω·cm) of Si substrate to fabricate PSi‐S is a low cost solution for the industry. In this paper, through an atomic force microscopy (AFM) analysis, the root mean square (RMS) roughness, the power spectral density and the correlation length were determined for different PSi layers. Furthermore, the measured hardness, Young's modulus, and stress have been made for different thicknesses of PSi: 5, 10, 50, and 200 μm. The obtained results demonstrated that very interesting properties have been achieved with the 50 μm‐thick PSi‐S layer with a maximum porosity around 65%, a surface roughness less than 1 nm and a hardness value of (~1 GPa). The realized results encourage the utilization the PSi‐based substrate into the industry process and thus the development of a Systems‐on‐Chip (SoC).

The interest of 5G in centimeter and millimeter waves relies on large blocks of available spectra and thus increased bandwidth. At these frequencies, the dielectric and conductive losses of the substrate can greatly degrade the performances of RF circuits. With high electrical resistivity and low relative permittivity, porous silicon is an ideal candidate as a high-quality RF substrate. This paper presents an innovative technique of post device fabrication integration of porous silicon (POST-PSi) with the substrate. The frontside is not involved in porous layer growth and therefore the integrity of the RF circuitry is not impacted by the POST-PSi process. A comparison of the RF performances with benchmark trap-rich (TR) silicon- on-insulator (SOI) substrate is presented. In addition to its compatibility with standard microfabrication processes and stable final structure, POST-PSi provides characteristics of low losses, high isolation and very high linearity, unmatched by any other silicon-based substrate.

The interest of porous silicon (PSi) for RF applications has been widely demonstrated in many previous works. In most of them, PSi is integrated into the substrate during its fabrication (PRE-PSi) prior to a standard process (e.g. CMOS). Such PRE-PSi technology has major incompatibilities with foundry-level processes (mechanical instability during annealing, warp, bow, etc.). This paper presents an innovative technique of post device fabrication integration of porous silicon (POST-PSi) with the substrate to overcome these incompatibilities. Furthermore, the frontside is not involved in porous layer growth and therefore the integrity of the RF circuitry is not impacted by the POST-PSi process. Additionally, the novel technique allows for local porosification, enabling local pockets of high-quality RF PSi-substrate, beneath the RF devices of interest, to be embedded within a structurally stable silicon crystalline bulk. Similar to PRE-PSi, the POST-PSi substrates are produced by anodization starting from the most widespread highly doped milliohm-centimeter Si wafers. A comparison of the RF performances with various advanced trap-rich (TR) silicon-on-insulator (SOI) and PRE-PSi substrates are presented. In addition to its compatibility with standard microfabrication processes and stable final structure, POST-PSi provides characteristics of low losses, high isolation and very high linearity, unmatched by any other silicon-based substrate.

This paper focuses on the comparison of the RF performances of various advanced trap-rich (TR) siliconon-insulator (SOI) and porous silicon (PSi) substrates. The PSi substrates are produced by electroporisification starting either from cheap standard resistivity (10 Omega.cm) silicon (PSi-S) or from the most widespread highly doped milliohm-centimeter Si wafers (PSi-M). Through small-signal RF measurements, it is shown that TR-enhanced high-resistivity silicon and both types of PSi are acceptable for RF applications, showing high effective resistivities and low RF substrate losses. What is more the substrate effective permittivity is decreased in the PSi substrates providing higher coupling isolation at high frequencies. Furthermore, large-signal harmonic distortion measurements reveal very strong linearity for both PSi substrates, with PSi-S achieving 50-dB improvement over the already highly linear TR substrate. Finally, RF characterization was carried out over temperature from 25 degrees C to 175 degrees C. While the performances of TR and PSi-M substrate rapidly deteriorate above 120 degrees C, the cost-effective PSi-S substrate maintains high performance all the way up to 175 degrees C, allowing it a wider range of potential applications.

Porous silicon substrate is very promising for next generation wireless communication requiring the avoidance of high-frequency losses originating from the bulk silicon. In this work, new variants of porous silicon (PSi) substrates have been introduced. Through an experimental RF performance, the proposed PSi substrates have been compared with different silicon-based substrates, namely, standard silicon (Std), trap-rich (TR) and high resistivity (HR). All of the mentioned substrates have been fabricated where identical samples of CPW lines have been integrated on. The new PSi substrates have shown successful reduction in the substrate's effective relative permittivity to values as low as 3.7 and great increase in the substrate's effective resistivity to values higher than 7 k Omega cm. As a concept proof, a mm-wave bandpass filter (MBPF) centred at 27 GHz has been integrated on the investigated substrates. Compared with the conventional MBPF implemented on standard silicon-based substrates, the measured S-parameters of the PSi-based MBPF have shown high filtering performance, such as a reduction in insertion loss and an enhancement of the filter selectivity, with the joy of having the same filter performance by varying the temperature. Therefore, the efficiency of the proposed PSi substrates has been well highlighted. (C) 2017 Elsevier Ltd. All rights reserved.

Porous silicon has a particularly large surface area available in a limited volume, tens or hundreds of square meters in a cubic centimeter. This attractive property is used to concentrate a large number of surface reactions (such as physico-chemical adsorption of gases) in a small volume. With a simple and cheap fabrication, the porous silicon is an ideal candidate for gas sensing applications. In this work, new gas sensor architecture in macroporous silicon is presented. The development of this new architecture, based on chemiresistor principle has led to several technological innovations. Three aspects were particularly studied: 1. Integration of miniaturized metal electrode on macroporous silicon to improve the sensitivity of measurement and to enable miniaturization of the sensor. The fabrication process has focused on standard microfabrication techniques to enables the transfer of the sensors to an industrial valorization. 2. A masking technique for localized formation of macroporous silicon to eliminate the mask underetching during the anodization of the porous silicon. 3. The functionalization by palladium nanoparticles of macroporous silicon with metal electrode integrated on the surface, to increase the sensitivity and selectivity of hydrogen sensing.

Nanostructured porous silicon is very promising for RF applications by overcoming the high-frequency losses originating from the bulk silicon substrate. RF performance and non-linearity analysis of different silicon substrates including, porous (PSi), trap-rich (TR) high resistivity (HR) types are explored experimentally. The investigation is done by means of coplanar transmission lines (CPW) fabricated on these substrates. RF measurements of transmission lines demonstrate the successful reduction of the permittivity and increase of the resistivity of the PSi substrate. It also demonstrated that the insertion losses and linearity are efficiently enhanced.

We present an original two-step method for the deposition via precipitation of Pd nanoparticles into macroporous silicon. The method consists in immersing a macroporous silicon sample in a PdCl2/DMSO solution and then in annealing the sample at a high temperature. The impact of composition and concentration of the solution and annealing time on the nanoparticle characteristics is investigated. This method is compared to electroless plating, which is a standard method for the deposition of Pd nanoparticles. Scanning electron microscopy and computerized image processing are used to evaluate size, shape, surface density and deposition homogeneity of the Pd nanoparticles on the pore walls. Energy-dispersive x-ray spectroscopy (EDX) and x-ray photoelectron spectroscopy (XPS) analyses are used to evaluate the composition of the deposited nanoparticles. In contrast to electroless plating, the proposed method leads to homogeneously distributed Pd nanoparticles along the macropores depth with a surface density that increases proportionally with the PdCl2 concentration. Moreover EDX and XPS analysis showed that the nanoparticles are composed of Pd in its metallic state, while nanoparticles deposited by electroless plating are composed of both metallic Pd and PdO x .

Methane and carbon dioxide activation play a major role in catalysis processes like dry reforming, syngas production and others. Any valorisation of CO2 and CH4 must take into account that they are strong greenhouse gases. CO2 and CH4 are also the main compounds of biogas. The combustion of which is a source of electricity in combined heat-power cogeneration plant (CHP).Our present efforts are devoted to design a catalytic sensor for biogas analysis. In such a sensor , both gases have to be activated at room temperature, which has been demonstrated as possible with cobalt based oxide. However, the deposition of the active phase on a silicon support needs a special attention, in order to provide the highest possible surface to increase the number of active site, while offering the guarantee that the active phase won’t be easily removed during the sensor functioning

This paper demonstrates the monolithic integration of an airflow sensor based on out-of-plane movable cantilevers with a CMOS integrated circuit providing small footprint and low-power sensing. Airflow is sensed by mechanical deflection of cantilevers without static power consumption contrary to classical thermal flow sensors based on micro-heater. The interfacing circuit is a CMOS ring oscillator (RO), fabricated on the same chip with silicon-on-insulator (SOI) technology, offering unique properties such as harsh environment resistance and lower power consumption. Moreover, the additional post-processing steps required by the built-in of out-of-plane cantilevers are minimum thanks to the use of standard CMOS materials and dry etching of the sacrificial layer.The developed microsystem demonstrates 10% variation of the RO frequency for an airflow varying from 0 m/s to 120 m/s, with a static power consumption of the order of 1 mu W. (C) 2013 Elsevier B.V. All rights reserved.

Macroporous silicon (MPS) has been demonstrated as an interesting material to be used in different applications including micromachining and chemical sensing. In most of these applications the formation of MPS in patterned areas is required or preferable. In this work we report the results of a study on the selective anodization of patterned p-type silicon substrates to form thick MPS layers. Two challenging issues were identified: (1) overetching at the edge of Si3N4 layers, which causes are principally associated with the electrical properties of the interface between the mask and the substrate and the distribution of carriers across the patterned area; (2) adherence of organic masking layers at the silicon during the anodization. Metallic Au/Ti masking layer was demonstrated to be a valuable solution to both issues. SEM cross-sectional views of macroporous layers formed on silicon substrates patterned using different materials are shown and analyzed. Experimental results are supported by two-dimensional (2D) simulations of the silicon/mask/electrolyte interface.