Modern multicore microprocessors require attentive development to energy requirements when maximizing power-performance efficiency and ensuring reliable plus scalable functionality. IBM POWER9 relies on extensive modeling to identify representative workloads used when analyzing thermal design power and regulator design power against product requirements. Compounding benefits of circuit optimizations applied to the diverse subcomponents of the chip results in lower power cores, caches, and memory/IO interconnect. Specific dc- and ac-current analyses ensure proper definition of chip specifications for system voltage and current delivery. Finally, a systematic exploration of microbenchmarks on intermediate and final POWER9 hardware provides insight into processor core requirements while validating model accuracy.

The two chips at the heart of the IBM z13™ system include a processor chip (referred to as the CP or Central Processor chip) and an L4 (Level 4) cache chip (referred to as the SC or System Controller chip), each 678 mm2 in area. The CP and SC chips were implemented with approximately 4 billion (4 × 109) and 7.1 billion transistors, respectively, in IBM's 22-nm SOI (silicon-on-insulator) technology, supporting eDRAM (embedded dynamic random access memory), and with up to 17 levels of metal available. In this paper, we discuss aspects of the circuit and physical design of these chips, including both digital logic and custom array implementation. In addition, we describe the design analysis methodology, along with some of the checks needed to ensure a robust, reliable, and high-frequency product.

This work describes the circuit and physical design implementation of the processor chip (CP), level-4 cache chip (SC), and the multi-chip module at the heart of the EC12 system. The chips were implemented in IBM's high-performance 32nm high-k/metal-gate SOI technology. The CP chip contains 6 super-scalar, out-of-order processor cores, running at 5.5 GHz, while the SC chip contains 192 MB of eDRAM cache. Six CP chips and two SC chips are mounted on a high-performance glass-ceramic substrate, which provides high-bandwidth, low-latency interconnections. Various aspects of the design are explored in detail, with most of the focus on the CP chip, including the circuit design implementation, clocking, thermal modeling, reliability, frequency tuning, and comparison to the previous design in 45nm technology.

This paper describes the circuit and physical design features of the z196 processor chip, implemented in a 45 nm SOI technology. The chip contains 4 super-scalar, out-of-order processor cores, running at 5.2 GHz, on a die with an area of 512 mm 2 containing an estimated 1.4 billion transistors. The core and chip design methodology and specific design features are presented, focusing on techniques used to enable high-frequency operation. In addition, chip power, IR drop, and supply noise are discussed, being key design focus areas. The chip's ground-breaking RAS features are also described, engineered for maximum reliability and system stability.

To reduce the product development time and achieve first-pass silicon success, fast and accurate estimation of very-large-scale integration (VLSI) interconnect, packaging and 3DI (3D integrated circuits) thermal profiles has become important. Present commercial thermal analysis tools are incapable of handling very complex structures and have integration difficulties with existing design flows. Many analytical thermal models, which could provide fast estimates, are either too specific or oversimplified. This paper highlights a methodology, which exploits electrical resistance solvers for thermal simulation, to allow acquisition of thermal profiles of complex structures with good accuracy and reasonable computation cost. Moreover, a novel accurate closed-form thermal model is developed. The model allows an isotropic or anisotropic equivalent medium to replace the noncritical back-end-of-line (BEOL) regions so that the simulation complexity is dramatically reduced. Using these techniques, this paper introduces the thermal modeling of practical complex VLSI structures to facilitate thermal guideline generation. It also demonstrates the benefits of the proposed anisotropic equivalent medium approximation for real VLSI structures in terms of the accuracy and computational cost.

In this talk, we will introduce a novel methodology using existing electromagnetic modelling tools for interconnect and packaging structures to simulate and model the temperature distribution without major modifications to these tools or simulated structures. This methodology can easily be integrated with the chip technology information and frame an electrical circuit simulator into an automatic, template-based simulation and optimization flow. A new accurate closed-form thermal model is further developed to simplify unnecessary object details. The model allows an equivalent medium with effective thermal conductivity (isotropic or anisotropic) to replace details in non-critical regions accurately so that complex interconnect structures can be simulated at a system level. Using these techniques, we demonstrate the modelling capability of very complex on-chip interconnects, packaging, and 3D integration technologies.

Accurate and fast estimation of VLSI interconnect thermal profiles has become critically important to estimate their impact on circuit/system performance and reliability, which is necessary for reducing product development time and achieving first-pass silicon success. Present commercial thermal analysis tools are incapable of simulating complex structures, particularly in the 3-D domain and are also difficult to integrate with existing design tools. Existing analytical thermal models are not perfect either: they are either not accurate enough or oversimplified. This paper uses a methodology, which exploits existing electrical resistance solvers for thermal simulation, to allow fast acquisition of thermal profiles of complex interconnect structures with good accuracy and reasonable computation cost. Moreover, for the first time, an accurate closed-form thermal model is developed. The model allows for an equivalent medium with effective thermal conductivity (isotropic or anisotropic) to replace the detailed material information in non-critical regions so that complex interconnect structures can be simulated. Using these techniques, this paper demonstrates the simulation of a very complex interconnect structure (~9000 objects or 15 million meshed unknowns after first order isotropic equivalent medium replacement), which is a first time achievement in the area of interconnect thermal analysis. On the other hand, it is shown that an anisotropic equivalent medium is a much better approximation of real interconnect structures from the point of view of accuracy and computation.

The IBM POWER6™ microprocessor is a 790 million-transistor chip that runs at a clock frequency of greater than 4 GHz. The complexity and size of the POWER6 microprocessor, together with its high operating frequency, present a number of significant challenges. This paper describes the physical design and design methodology of the POWER6 processor. Emphasis is placed on aspects of the design methodology, technology, clock distribution, integration, chip analysis, power and performance, random logic macro (RLM), and design data management processes that enabled the design to be completed and the project goals to be met.

A parallel LU decomposition algorithm is presented to take advantage of the sparse impedance matrix produced by the reduced-coupling method. This algorithm allows rapid simulation of very large chip and packaging problems. A representative example is shown for a wide, on-chip data-bus that required one million surface unknowns and the computational power of a 1024-node IBM BlueGene cluster with distributed memory.

This paper discusses the effects of the frequency-dependent losses in the reference return path for wide, on-chip data buses, that must be understood in order to accurately predict the interaction and summation of crosstalk and common-mode noise signals. This interaction can generate excessive noise for on-chip global interconnections. Measured and simulated results are shown for representative 8-12 line couplings and circuit-synthesis techniques are shown to capture the correct R(f)L(f)C behavior of the reference series impedance.