The IBM Z microprocessor in the z14 system has been redesigned to improve performance, system capacity, and security [1] over the previous z13 system [2]. The system contains up to 24 central processor (CP) and 4 system controller (SC) chips. Each CP, shown in die photo A (Fig. 2.2.7), operates at 5.2GHz and is comprised of 10 cores, 2 PCIe Gen3 interfaces, an IO bus controller (GX), 128MB of L3 embedded DRAM (eDRAM) cache, X-BUS interfaces connecting to 2 other CP chips and one SC chip, and a redundant array of independent memory (RAIM) interface. Each core on the CP chip has 4MB of eDRAM L2 Data cache and 2MB of eDRAM L2 Instruction cache, with 128KB SRAM Instruction and 128KB SRAM Data L1 caches. Each SC, shown in die photo B (Fig. 2.2.7), operates at 2.6GHz and has 672MB of L4 eDRAM cache, X-BUS interfaces connecting to CP chips in the drawer and A-BUS interfaces connecting SCs on the other drawers. Both chips are 696mm 2 and are designed in Global Foundries 14nm high performance (14HP) SOI FinFET technology with 17 layers of copper interconnect [3]. The CP contains 6.1B transistors, while the SC contains 9.7B transistors. The total IO bandwidth of the CP and SC are 2.9Tb/s and 5.5Tb/s, respectively.

Pulsed latches that are widely used in high performance circuits are susceptible to early mode failures. High performance circuits also experience higher voltage and temperature conditions that exacerbates device degradation due to mechanisms such as BTI and HCI. In this paper, the impact of aging on hold slack in pulsed latches is presented. Analysis of clock gating that leads to AC or DC stress in the pulse generation circuits is illustrated, and the need to provide additional hold margin for these effects is demonstrated.

In designing the IBM z14 microprocessor chipset, we discarded many of our previous assumptions and processes in favor of newer, more radical approaches. These new approaches were the result of learning from previous designs as well as this design's performance and schedule requirements. In this paper, we discuss some of the more significant changes to our methodology, including a dramatic departure from our very hierarchical integration design style to a flatter, more nimble approach. We also discuss improvements to our design's power management architecture for managing power-supply noise. Finally, we discuss changes to our simulation environment, targeted at increasing both the number of simulation cycles and simulation logic coverage.

The IBM z14 design was built with the 14-nm high performance silicon-on-insulator (SOI) technology of GLOBALFOUNDRIES. This was the first technology node after IBM transitioned from its integrated fabrication facility to operating in a fabless environment, driving significant changes to design processes and methodology. In addition to this partnership, the 14-nm technology introduced significant changes relative to previous technology nodes, including the introduction of fin-shaped field-effect transistors, the use of double patterning for the lowest back-end-of-line layers, and the introduction of middle-of-line layers to exploit contact layers for local interconnects. This combination of technical and business challenges required numerous large-scale innovations for our design, design team, and design methodologies. In this paper, we provide a survey of these innovations, including the fin-based standard cell image, deeply scaled SOI self-heating/electromigration verification, routing strategies to handle double-patterning with interlayer via awareness, fill automation to enable simultaneous design of multiple layers of hierarchy, and high-performance array design with the voltage and noise limitations of the 14-nm technology node.

This paper presents a novel technique to optimize the design of non-conventional tapered and skewed standard cell gates, and the synthesis algorithms for efficient usage of such gates in IBMs high-performance 22nm CMOS SOI technology. The focus is on design considerations to ensure that synthesis can use these gates efficiently, leveraging the resulting timing improvements for faster timing closure of high-performance microprocessor designs. A detailed analysis is presented, where by exposing these gates to synthesis at different points in the process, the optimal point of insertion is identified. Also an efficient algorithm is proposed to handle decisions regarding the conversion of conventional gates to non-conventional gates, after taking into account multiple factors including delay and slew. Results show 25 - 30% improvement in total negative slack of designs and 20 - 25% reduction in the total number of negative paths, without any major impact on total power of the designs.

While great efforts have been made to counter the EM reliability degradation due to technology scaling, closer cooperation is needed among semiconductor fabricators, circuit/chip designers and system integrators to ensure final product reliability. This paper presents an example of systematic EM reliability evaluation from design point definition to chip design verification, to system characterization, and finally to EM reliability monitoring from in-field operations.

James Warnock, Brian Curran, John Badar, Gregory Fredeman, Donald Plass, Yuen Chan, Sean Carey, Gerard Salem, Friedrich Schroeder, Frank Malgioglio, Guenter Mayer, Christopher Berry, Michael Wood, Yiu-Hing Chan, Mark Mayo, John Isakson, Charudhattan Nagarajan, Tobias Werner, Leon Sigal, Ricardo Nigaglioni, Mark Cichanowski, Jeffrey Zitz, Matthew Ziegler, Tim Bronson, Gerald Strevig, Daniel Dreps, Ruchir Puri, Douglas Malone, Dieter Wendel, Pak-Kin Mak, Michael Blake

The IBM POWER8™ processor is a 649-mm2, 4.2-billion transistor, high-frequency microprocessor fabricated in the IBM 22-nm silicon on insulator (SOI) technology with embedded dynamic random access memory (eDRAM) and 15 layers of metal. With its twelve architecturally enhanced, eight-way multithreaded cores, 96-MB high-bandwidth shared third-level cache, and increased on and off-chip bandwidth, the POWER8 processor delivers industry-leading performance. This paper describes the circuit techniques and design methodologies that were employed for implementing this chip and that allowed it to maintain the power dissipation at the level of its predecessor while delivering a threefold increase in per-socket performance. Among the innovative technologies employed by the processor are resonant clocking, on-chip per-core voltage regulation, and enhanced eDRAM arrays.

POWER8™ is a 12-core processor fabricated in IBM's 22 nm SOI technology with core and cache improvements driven by big data applications, providing 2.5× socket performance over POWER7+™. Core throughput is supported by 7.6 Tb/s of off-chip I/O bandwidth which is provided by three primary interfaces, including two new variants of Elastic Interface as well as embedded PCI Gen-3. Power efficiency is improved with several techniques. An on-chip controller based on an embedded PowerPC™ 405 processor applies per-core DVFS by adjusting DPLLs and fully integrated voltage regulators. Each voltage regulator is a highly distributed system of digitally controlled microregulators, which achieves a peak power efficiency of 90.5%. A wide frequency range resonant clock design is used in 13 clock meshes and demonstrates a minimum power savings of 4%. Power and delay efficiency is achieved through the use of pulsed-clock latches, which require statistical validation to ensure robust yield.

The next-generation System z design introduces a new microprocessor chip (CP) and a system controller chip (SC) aimed at providing a substantial boost to maximum system capacity and performance compared to the previous zEC12 design in 32nm [1,2]. As shown in the die photo, the CP chip includes 8 high-frequency processor cores, 64MB of eDRAM L3 cache, interface IOs (“XBUS”) to connect to two other processor chips and the L4 cache chip, along with memory interfaces, 2 PCIe Gen3 interfaces, and an I/O bus controller (GX). The design is implemented on a 678 mm2 die with 4.0 billion transistors and 17 levels of metal interconnect in IBM's high-performance 22nm high-x CMOS SOI technology [3]. The SC chip is also a 678 mm2 die, with 7.1 billion transistors, running at half the clock frequency of the CP chip, in the same 22nm technology, but with 15 levels of metal. It provides 480 MB of eDRAM L4 cache, an increase of more than 2× from zEC12 [1,2], and contains an 18 MB eDRAM L4 directory, along with multi-processor cache control/coherency logic to manage inter-processor and system-level communications. Both the CP and SC chips incorporate significant logical, physical, and electrical design innovations.

The two chips at the heart of the IBM z13™ system include a processor chip (referred to as the CP or Central Processor chip) and an L4 (Level 4) cache chip (referred to as the SC or System Controller chip), each 678 mm2 in area. The CP and SC chips were implemented with approximately 4 billion (4 × 109) and 7.1 billion transistors, respectively, in IBM's 22-nm SOI (silicon-on-insulator) technology, supporting eDRAM (embedded dynamic random access memory), and with up to 17 levels of metal available. In this paper, we discuss aspects of the circuit and physical design of these chips, including both digital logic and custom array implementation. In addition, we describe the design analysis methodology, along with some of the checks needed to ensure a robust, reliable, and high-frequency product.

This work describes the circuit and physical design implementation of the processor chip (CP), level-4 cache chip (SC), and the multi-chip module at the heart of the EC12 system. The chips were implemented in IBM's high-performance 32nm high-k/metal-gate SOI technology. The CP chip contains 6 super-scalar, out-of-order processor cores, running at 5.5 GHz, while the SC chip contains 192 MB of eDRAM cache. Six CP chips and two SC chips are mounted on a high-performance glass-ceramic substrate, which provides high-bandwidth, low-latency interconnections. Various aspects of the design are explored in detail, with most of the focus on the CP chip, including the circuit design implementation, clocking, thermal modeling, reliability, frequency tuning, and comparison to the previous design in 45nm technology.

Reliability is a key concern for VLSI circuits especially so for latches and memories due to their small feature sizes. Particularly, for SRAM cell designs Bias Temperature Instability effects have significant implications on functionality and performance. Here we propose through simulation and modeling an efficient statistical methodology to evaluate and minimize the aging of memory chips. Redundancy has been typically used to resolve failing parts at beginning-of-life. In this approach, we propose to use redundancy to repair critical parts that are most susceptible to aging, thereby optimizing end-of-life yield. Our methodology enables what would have been a very expensive and exhaustive hardware testing approach by identifying optimal repair corners via fast statistical simulations. The methodology takes into consideration reliability effects in the presence of random process variation. This in turn identifies critical repair parts for optimal yield and helps minimize the ever increasing field failure problem.

As traditional CMOS scaling comes to an end, the industry is moving towards new 3D finFET multigate structures as device engineers stand the silicon transistors up on their sides. Digital circuit designers working in the 14nm technology node will face significant new challenges from additional design constraints and new sources of variability associated with this non-planar transistor structure. In addition, computational lithography and the need for double patterning at the 14nm node will drive up the complexity and difficulty of the physical design implementation, pushing designs towards more uniform and regular structures, even as wire RC and reliability issues drive increasing demand for uniquely customized solutions. New design tools and methodologies will therefore be needed to meet these circuit and PD challenges at the 14nm node.

The new System z microprocessor chip (“CP chip”) features a high-frequency processor core running at 5.5GHz in a 32nm high-κ CMOS technology [1], using 15 levels of metal. This chip is a successor to the 45nm product [2], with significant improvements made to the core and nest (i.e. the logic external to the cores) in order to increase the performance and throughput of the design. Also, special considerations were necessary to ensure robust circuit operation in the high-κ technology used for implementation. As seen in the die photo, the chip contains 6 processor cores (compared to 4 cores in the 45nm version), and a large shared 48MB DRAM L3 cache. Each core includes a pair of data and instruction L2 SRAM caches of 1MB each. In addition, the chip contains a memory control unit (MCU), an I/O bus controller (GX), and two sets of interfaces to the L4 cache chips (also in 32nm technology). The CP chip occupies 598 mm2, contains about 2.75B transistors, and has 1071 signal IOs.

This paper describes the circuit and physical design features of the z196 processor chip, implemented in a 45 nm SOI technology. The chip contains 4 super-scalar, out-of-order processor cores, running at 5.2 GHz, on a die with an area of 512 mm 2 containing an estimated 1.4 billion transistors. The core and chip design methodology and specific design features are presented, focusing on techniques used to enable high-frequency operation. In addition, chip power, IR drop, and supply noise are discussed, being key design focus areas. The chip's ground-breaking RAS features are also described, engineered for maximum reliability and system stability.

Technology scaling has provided the semiconductor industry a recipe to successfully meet the application demands for performance for over three decades. This computational capacity was further fueled by the success of circuit and architecture-level innovation, which provided performance improvement in each processor generation. However, future processor designs face a number of key challenges in sustaining the growth trends. The dawn of the 22nm node, and beyond, marks an era of new trends and challenges; where the cost and complexity associated with each technology node is increasing at much faster rate than the device performance gains. Novel tools and design methodologies are needed to not only compensate for these challenges but also to leverage emerging technologies to achieve the desired performance in future processor architectures. Technology alternatives such as 3D integration have attracted significant interest as an additional way of sustaining the density scaling and performance growth. 3D integration provides some unique benefits for processor design, such as packaging density, interconnect bandwidth and latency, modularity, and heterogeneity. Packaging density improvement provided by 3D can be used to continue improvements in processing and storage capacity as well as enabling a gradual shift towards integrating the full system in one stack. Through-Silicon-Vias (TSVs) provide lower latency and higher bandwidth that improves interconnect-limited performance. 3D enables modular design of a variety of systems from a shared set of sub-components through functional separation of the device layers. As a result, different layers can be independently manufactured in the most cost effective ways, which can be stacked to compose a wide range of customized systems. Optimizing layer interfaces and infrastructure components, such as power delivery and clocking, can further enhance the inherent modularity advantages. 3D provides opportunities for composing future s- - ystems by integrating disparate technologies as well as different technology generations in the same stack. It can be used to incorporate a wide range of device layers including non-volatile memory layers, MEMS, FPGAs, DRAM or photonics in the same stack, easing the IO/off-chip bandwidth limitations. This provides the opportunity to enable processor architectures with new computation, storage and communication capabilities. The system-level benefits of 3D will be determined, to a significant degree, by the effectiveness of novel design methodologies that explore the new design space introduced by the vertical dimension. Design flow optimization is essential in achieving the highest performance gains as well as tackling the more prominent interdependencies among performance, power dissipation, temperatures, interconnectivity and reliability in 3D. This presentation will highlight these challenges and opportunities.

The zEnterprise 196 is the latest IBM System zSeries mainframe computer, which builds on IBM's 46-year heritage of compatible enterprise-class machines. This design advances the prior z10 processor pipeline with out-of-order execution to achieve considerable performance gains in legacy online transaction processing and computationally intensive workloads. This article describes the system structure and details of this new high-frequency microprocessor.