Nonvolatile flip-flops and latches have been proposed as key building blocks for improving the reliability and energy efficiency of computing systems operating under aggressive power gating and intermittent power availability. Ferroelectric field-effect transistors (FeFETs) based on van der Waals (vdW) heterostructures provide a promising approach for nonvolatile sequential logic by enabling direct integration of memory functionality into logic devices while minimizing interface-related degradation. In this work, CuInP2S6-based vdW FeFETs are fabricated in both metal-ferroelectric-metal-insulator-semiconductor and metal-ferroelectric-semiconductor configurations, exhibiting robust ferroelectric switching and stable nonvolatile behavior. Building on these devices, ferroelectric nonvolatile inverters are realized, followed by a nonvolatile ferroelectric latch that reliably restores its logic state after complete power loss. The proposed latch leverages ambipolar MoTe2 channels to inherently drive the FeFET gate-source and gate-drain voltages to full rail-to-rail values (VGS = VGD = ±VDD) in a state-dependent manner, thereby ensuring reliable polarization switching without auxiliary sensing circuitry or additional bias-management schemes. Owing to the clean vdW interfaces and intrinsic circuit operation, the latch restores its state upon power recovery using only simple control signals. These results demonstrate the strong performance of 2D vdW FeFETs and establish nonvolatile latch operation as a viable experimental platform for nonvolatile sequential logic and energy-efficient computing architectures.

Emerging applications in data-intensive computing and circuit security demand logic circuits with high functional density, reconfigurability, and energy efficiency. Here, we demonstrate nonvolatile reconfigurable four-mode field-effect transistors (NVR4M-FETs) based on two-dimensional (2D) MoTe2 and CuInP2S6 (CIPS), offering both polarity switching and threshold voltage modulation. The device exploits the ferroelectric polarization of CIPS at the source/drain regions to achieve dynamic control over the transistor polarity, enabling transitions between n-type and p-type states through polarization-induced local electrostatic doping. Additionally, multilayer graphene floating gates are incorporated to modulate the threshold voltage, yielding four distinct nonvolatile operating modes: n-type logic, p-type logic, always-on memory, and always-off memory. Leveraging the four-mode property, the NVR4M-FET can function as a one-transistor-per-bit ternary content-addressable memory (TCAM). In addition, we demonstrate the construction of transformable logic gates with 14 distinct logic functions using two NVR4M-FETs and a reconfigurable half a dder/subtractor using three NVR4M-FETs integrated with load resistors. Furthermore, we show that a 2-input look-up table can be achieved with eight NVR4M-FETs compared to 12 transistors using reconfigurable transistors, highlighting the potential of NVR4M-FETs for high-density logic circuits. These results underscore the potential of NVR4M-FETs as essential building blocks for energy-efficient, in-memory computing, and secure hardware applications.

As a promising alternative to the Von Neumann architecture, in-memory computing holds the promise of delivering high computing capacity while consuming low power. Content addressable memory (CAM) can implement pattern matching and distance measurement in memory with massive parallelism, making them highly desirable for data-intensive applications. In this paper, we propose and demonstrate a novel 1-transistor-per-bit CAM based on the ferroelectric reconfigurable transistor. By exploiting the switchable polarity of the ferroelectric reconfigurable transistor, XOR/XNOR-like matching operation in CAM can be realized in a single transistor. By eliminating the need for the complementary circuit, these non-volatile CAMs based on reconfigurable transistors can offer a significant improvement in area and energy efficiency compared to conventional CAMs. NAND- and NOR-arrays of CAMs are also demonstrated, which enable multi-bit matching in a single reading operation. In addition, the NOR array of CAM cells effectively measures the Hamming distance between the input query and stored entries. Furthermore, utilizing the switchable polarity of these ferroelectric Schottky barrier transistors, we demonstrate reconfigurable logic gates with NAND/NOR dual functions, whose input-output mapping can be transformed in real-time without changing the layout. These reconfigurable circuits will serve as important building blocks for high-density data-stream processors and reconfigurable Application-Specific Integrated Circuits (r-ASICs). The CAMs and transformable logic gates based on ferroelectric reconfigurable transistors will have broad applications in data-intensive applications from image processing to machine learning and artificial intelligence.

High -temperature operation of the p-GaN gate high -electron -mobility transistor (HEMT) was investigated, specifically up to 500 degrees C. The p-GaN gate HEMT demonstrated stable behavior with normally -off operation, steep increase of drain current in the subthreshold region, and suppressed off -state current. By adding Al2O3 etch -stop layer, the device showed significant reduction in subthreshold swing when measured at 500 degrees C, effectively mitigating hysteresis in the transfer characteristics. Additionally, the lifetime of the gate stack with the etch -stop layer was estimated to be much longer than that of the stack without the etch -stop layer. Through the integration of the depletion -mode (D -mode) metal -insulator -semiconductor HEMT (MIS-HEMT) device with the p-GaN gate device, a direct -coupled field-effect transistor logic (DCFL) inverter was fabricated. This inverter showed stable logic operation up to 500 degrees C, featuring rail -to -rail operation and large gain. A long-term reliability test conducted at 500 degrees C for 100 hours revealed stabilized on -state and off -state values after about 50 hours of operation.

In this paper, we demonstrate low-thermal-budget ferroelectric field-effect transistors (FeFETs) based on the two-dimensional ferroelectric CuInP2S6 (CIPS) and oxide semiconductor InZnO (IZO). The CIPS/IZO FeFETs exhibit nonvolatile memory windows of ∼1 V, low off-state drain currents, and high carrier mobilities. The ferroelectric CIPS layer serves a dual purpose by providing electrostatic doping in IZO and acting as a passivation layer for the IZO channel. We also investigate the CIPS/IZO FeFETs as artificial synaptic devices for neural networks. The CIPS/IZO synapse demonstrates a sizable dynamic ratio (125) and maintains stable multilevel states. Neural networks based on CIPS/IZO FeFETs achieve an accuracy rate of over 80% in recognizing MNIST handwritten digits. These ferroelectric transistors can be vertically stacked on silicon complementary metal-oxide semiconductor (CMOS) with a low thermal budget, offering broad applications in CMOS+X technologies and energy-efficient 3D neural networks.

High temperature operation of enhancement-mode (E-mode) and depletion-mode (D-mode) AlGaN/GaN metal-insulator-semiconductor high-electron-mobility transistors (MIS-HEMTs) was demonstrated. By using the circular device structure, off-state current was effectively suppressed, and record high Ion/Ioff ratio around 108 was obtained at 400 °C. Atomic layer etching was used for formation of the gate recess structure in the E-mode device, and good interface was made which enabled stable normally-off operation up to 400 °C. D-mode device experienced positive threshold voltage shift during the high temperature operation and after cooling down to room temperature, due to strain relaxation. On the other hand, due to the very thin AlGaN layer retained under the gate of the E-mode device, the threshold voltage of the E-mode device is nearly unchanged when the sample is heated up and cooled down. A direct coupled field-effect transistor logic (DCFL) inverter was fabricated based on the E-mode and D-mode devices and showed stable operation up to 400 °C.

AlGaN/GaN metal–insulator–semiconductor high-electron-mobility transistors (MIS-HEMTs) were demonstrated to operate at temperatures of up to 600 °C. High-quality multilayer gate dielectrics (Al2O3/SiO2/SiON) were developed to enhance the thermal stability of the MIS-HEMTs at high temperatures. Furthermore, we found that silicon nitride passivation and circular structure can effectively reduce the off-state drain current, which is critical for high-temperature operations. Based on the optimized process, we demonstrated the AlGaN/GaN MIS-HEMTs with record high Ion/Ioff ratios (1011 at room temperature and 105 at 600 °C) and high transconductances (47 mS/mm at room temperature and 8 mS/mm at 600 °C for a channel length of 2.4 μm). The maximum transconductance was enhanced by ∼28% after the operation at 600 °C. Lifetime measurement of the MIS-HEMT showed stable DC characteristics with a nearly unchanged on-state drain current and threshold voltage over the course of 25-h thermal stress at 525 °C.

Unlike transitional semiconductors, graphene has zero bandgap and symmetric electron/hole transport, which leads to unique V-shaped transfer characteristics. Using this property, we design and demonstrate a new type of comparator, which can calculate the absolute distance between two signals, |A - B|, directly. Dual-gate graphene transistors with ferroelectric hafnium zirconium oxide are fabricated to serve as the basic units of the comparators. We show that the remanent polarization of the ferroelectric hafnium oxide can reach ~30 μC/cm 2 and the output current of the comparator can serve as a scalar indicator of the similarity level between two signals. The embedded ferroelectric layer can store the reference signal in situ, which will reduce the energy consumption and latency related to the data transport. Furthermore, we demonstrate the feasibility of using ferroelectric graphene comparator in image classification and motion detection. Using the k-nearest neighbors (KNNs) algorithm, we show that the graphene comparator arrays can recognize the handwritten digits in the modified national institute of standards and technology (MNIST) data set with over 80% accuracy. These ferroelectric graphene comparators will have broad applications in robotics, security system, self-driving vehicles, and sensor networks.

Van der Waals (vdW) ferroelectric insulator CuInP2S6 (CIPS) has attracted intense research interest due to its unique ferroelectric and piezoelectric properties. In this paper, we systematically investigate the temperature and frequency dependence of the ferroelectric properties of CIPS. We find that there is a large imprint in the CIPS capacitor, which can be attributed to the fixed dipoles induced by defects. At high temperatures and low frequencies, the amplitude and direction of the imprint become tunable by the preset pulse, as the copper ions are more mobile and these dipoles become switchable. When the polarization in CIPS changes direction, the graphene/CIPS/graphene ferroelectric diode exhibits switchable resistance since the Fermi level in graphene is modulated by the polarization in CIPS. For CIPS/MoTe2 dual-gate transistor, a temperature-dependent nonvolatile memory window is observed, which can be attributed to the interplay between ferroelectric polarization and interface traps. This research provides experimental groundwork for vdW ferroelectric materials, expands the understanding of ferroelectricity in CIPS, and opens up exciting opportunities for novel electronic devices based on vdW ferroelectric materials.

Introducing ferroelectricity to two-dimensional van der Waals (vdW) materials such as graphene, transition metal dichalcogenides, and black phosphorous presents a promising route for developing high-speed and low-power nanoelectronics. This Perspective reviews two actively pursued materials strategies, ferroelectric/vdW heterostructures and vdW ferroelectric materials. The topics discussed include their application potential and performance limitations as memory, logic, sensing, and optical devices, as well as the challenges and outlook of the field.

Ferroelectric tunneling junctions (FTJs) with tunable tunneling electroresistance (TER) are promising for many emerging applications, including non-volatile memories and neurosynaptic computing. One of the key challenges in FTJs is the balance between the polarization value and the tunneling current. In order to achieve a sizable on-current, the thickness of the ferroelectric layer needs to be scaled down below 5 nm. However, the polarization in these ultra-thin ferroelectric layers is very small, which leads to a low tunneling electroresistance (TER) ratio. In this paper, we propose and demonstrate a new type of FTJ based on metal/Al2O3/Zr-doped HfO2/Si structure. The interfacial Al2O3 layer and silicon substrate enable sizable TERs even when the thickness of Zr-doped HfO2 (HZO) is above 10 nm. We found that F-N tunneling dominates at read voltages and that the polarization switching in HZO can alter the effective tunneling barrier height and tune the tunneling resistance. The FTJ synapses based on Al2O3/HZO stacks show symmetric potentiation/depression characteristics and widely tunable conductance. We also show that spike-timing-dependent plasticity (STDP) can be harnessed from HZO based FTJs. These novel FTJs will have high potential in non-volatile memories and neural network applications.

Ferroelectric tunneling junctions (FTJs) with tunable tunneling electroresistance (TER) are promising for many emerging applications including non-volatile memories and neurosynaptic computing. Traditional FTJs were mainly based on perovskites, such as lead zirconate titanate (PZT). Recently, doped hafnium oxide (HfO 2 ) emerged as a new class of ferroelectric materials [1]. As compared to traditional perovskites, doped HfO 2 has the advantages of high coercive field and full compatibility with CMOS processes. Among various doped HfO 2 , Zr-doped HfO 2 (HZO) is particularly attractive due to its low annealing temperature and excellent scalability [2]-[3]. In FTJs based on metal/HZO/metal structure, in order to achieve a sizable on-current, the thickness of HZO needs to be scaled down below 5 nm. However, the polarization in these ultra-thin HZO film is very small, which leads to a low TER ratio [4]. In this project, we propose and demonstrate a new type of FTJ based on metal/Al 2 O 3 /HZO/Si structure. The interfacial Al 2 O 3 layer and semiconducting substrate enable sizable TERs even when the thickness of HZO is above 10 nm. We demonstrate FTJ synapses with symmetric potentiation and depression characteristics and widely tunable conductance. We also show that spike-timing-dependent plasticity (STDP) can be harnessed from HZO based FTJs.

In this paper, we explore new metal electrodes for ferroelectric capacitors based on Al-doped HfO2. We find that Ti/Pd, Ti/Au, and W top electrodes can induce much higher remanent polarization as compared to the traditional TiN top electrode. The endurance of the capacitors with Ti/Pd electrodes is also much better than that with TiN and W electrodes. These results indicate that Ti/Pd is a very promising candidate for ferroelectric Al-doped HfO2. In addition, we find that the remanent polarization reaches maximum when the annealing temperature is around 900 degrees C-950 degrees C. At a given annealing temperature, the optimal Hf-to-Al cycle ratio corresponding to the highest remanent polarization is around 23:1. With optimized process conditions, we demonstrate high-performance Ti/Pd gated ferroelectric Al-doped HfO2 capacitors with remanent polarization up to 20 mu C/cm(2), endurance higher than 10(8) cycles, and retention over ten years at room temperature. Another interesting feature of the ferroelectric capacitors with Ti/Pd electrodes is high tunability of polarization by external pulses, which will be important for neurosynaptic computing applications.

In this paper, we review our research on nanoscale electronic and optoelectronic devices based on two-dimensional (2D) materials and ferroelectric materials. Our study reveals that the current transport in graphene is highly influenced by the number of layers, local topography, and gate dielectrics on the graphene. High-performance radio-frequency (RF) devices and plasmonic photodetectors were fabricated based on graphene. We also synthesized monolayer molybdenum disulfide (MoS 2 ) and tungsten diselenide (WSe 2 ) using chemical vapor deposition. The domain size of monolayer WSe 2 exceeds 100 μm. We demonstrate that logic devices based on MoS 2 have the potential to suppress short-channel effects and have high critical breakdown electric field. The gap states of MoS 2 were characterized using ac conductance. We found that the true band mobility of MoS 2 is much higher than the measured effective mobility due to the large number of gap states. In addition, we systematically investigated ferroelectric aluminum (Al)-doped hafnium oxide (HfO 2 ) with various top electrodes, Hf to Al ratios, and annealing temperatures. High-quality ferroelectric Al-doped HfO 2 with high remanent polarization and long endurance have been demonstrated.

Ferroelectric complex perovskites, such as lead zirconate titanate (PZT), strontium bismuth tantalate (SBT), and lead magnesium niobate-lead titanate (PMN-PT) have been widely used in ferroelectric devices. However, these traditional ferroelectric materials have a limitation in thickness scaling and are incompatible with CMOS processes. In the last few years, doped metal oxides, including hafnium oxide (HfO 2 ) and zirconium oxide (ZrO 2 ), were found to have ferroelectric phase [1]-[2]. Ferroelectric HfO 2 has the advantages of a high coercive field, excellent scalability (down to 2.5nm), and good compatibility with CMOS processing [3]-[7]. In this paper, we systematically investigate Al-doped HfO 2 with various electrodes, Al compositions and annealing temperatures. We found that Ti/Pd is a promising candidate as top electrode material for ferroelectric HfO 2 .